中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.019 seconds)

    Symmetric switching functions using magnetic bubble domains
    1.
    发明授权
    Symmetric switching functions using magnetic bubble domains 失效
    使用磁泡区域的对称开关功能

    公开(公告)号：US3919701A

    公开(公告)日：1975-11-11

    申请号：US35166573

    申请日：1973-04-16

    Applicant: IBM

    Inventor： CHANG HSU ,  CHEN TIEN CHI ,  TUNG CHIN

    IPC: G06F7/48 ,  G11C11/14 ,  H03K19/168 ,  G11C19/00

    CPC classification number: H03K19/168

    Abstract: A symmetric switching device which can be personalized to do any mathematical operation relying upon the mounting of the number of bubble domains present. This can be used as a universal logic element to provide any logical function. The device will handle multiple inputs and is rewritable to provide the desired function. The device broadly comprises a counter for counting the number of 1 bits in the input data stream, a means for producing a control data stream for personalizing the switch, and a comparison means for comparing the counter output and the control stream. A particularly suitable embodiment comprises a bubble domain sifter for shifting the position of the bubbles in the input data stream, a leading bubble detector for detecting the leading (first) bubble in the input data stream, means for creating a personalized control bubble stream for designating the function to be performed, and means for comparing the personalized control bubble stream with the output of the leading bubble detector to provide a circuit output representing the output value of the function desired. Means are provided for serial or parallel data inputs to the symmetric switching circuit. Any known type of domain propagation structure can be used to implement this device.

    Abstract translation: 一种对称开关装置，其可以被个性化以进行任何数学运算，这依赖于存在的气泡域的数量的安装。 这可以用作通用逻辑元件来提供任何逻辑功能。 该设备将处理多个输入，并且是可重写的，以提供所需的功能。 该设备广泛地包括用于对输入数据流中的1位数进行计数的计数器，用于产生用于个性化该开关的控制数据流的装置，以及用于比较计数器输出和控制流的比较装置。 特别合适的实施例包括用于移动输入数据流中的气泡位置的气泡域筛选器，用于检测输入数据流中的引导（第一）气泡的前导气泡检测器，用于创建个性化控制气泡流的装置，用于指定 要执行的功能，以及用于将个性化控制气泡流与前导气泡检测器的输出进行比较以提供表示所需功能的输出值的电路输出的装置。 提供用于对称开关电路的串行或并行数据输入的装置。 可以使用任何已知类型的域传播结构来实现该设备。

    Binary arithmetic unit implementing a multiplicative steration for the exponential, logarithm, quotient and square root functions
    2.
    发明授权
    Binary arithmetic unit implementing a multiplicative steration for the exponential, logarithm, quotient and square root functions 失效
    二进制算术单元执行多项式，逻辑，数量和方程函数的多项式

    公开(公告)号：US3631230A

    公开(公告)日：1971-12-28

    申请号：US3631230D

    申请日：1970-09-24

    Applicant: IBM

    Inventor： CHEN TIEN CHI

    IPC: G06F7/544 ,  G06F7/48 ,  G06F7/52

    CPC classification number: G06F7/544

    Abstract: Apparatus and a method is described for efficiently achieving arithmetic evaluations for functions such as exponential, logarithm, quotient, and square root with a minimum use of multiplications or divisions. Basically, use is made of the fact that x(1 + OR - 2 m) can be evaluated by a shift followed by an add. A pair of numbers (xk, yk) can represent a function x: f(x) g(xk, yk), such that g (l, yn) yn for logarithm, quotient and square root. Then, multiplication by shifting is applied to xk with suitable adjustments on yk, until xk is close to unity, at which time yk represents the desired answer. The exponential is computed by essentially reversing the logarithm procedure. A termination algorithm further improves accuracy. The apparatus involves two registers for xk and yk, a local memory, an adder and a shift register.

    6.
    发明专利
    未知

    公开(公告)号：FR2303348A1

    公开(公告)日：1976-10-01

    申请号：FR7602210

    申请日：1976-01-20

    Applicant: IBM

    Inventor： CHEN TIEN CHI ,  TUNG CHIN

    IPC: G11C11/14 ,  G11C19/08

    Abstract: An apparatus for performing efficient transposition exchange sorts among equal length records is described. The apparatus takes advantage of the flow steering property of linkable circulating storage loops to minimize the average access time by positioning information closer to the output port in a storage structure. The apparatus is formed from a linear array of equal size shift register loops each holding one record. The loops are switchably interconnected such that when two boundary switches are set in a first mode, the contents of each loop normally circulate wholly therewithin. Upon a common boundary switch being set in a second mode, the contents within a first loop flow into a second loop and vis-a-vis. By setting a common boundary switch to the second mode, the contents of a pair of adjacent loops are exchanged in the duration of one loop cycle time. Further exchanges can be started before a previous one is complete; this overlapping of operations can lead to an effective exchange rate of two exchanges per loop cycle. By repeating the exchange for consecutive pairs of loops, then the contents of any reference loop can be migrated to an output port D loops away in (D + 1)/2 loop cycle times.

    7.
    发明专利
    未知

    公开(公告)号：DE2361512A1

    公开(公告)日：1974-06-20

    申请号：DE2361512

    申请日：1973-12-11

    Applicant: IBM

    Inventor： CHEN TIEN CHI ,  HO IRVING TZE

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/493 ,  G06F7/499 ,  G06F11/10 ,  G06F11/02

    Abstract: A modulo 9 residue generating and checking circuit for checking the accuracy of decimal addition operations in digital computers and other data processing equipment. A set of data words each representing a number to be added is transmitted to a multi-number adder which adds the words and provides a smaller set of words as a subtotal sum. The bits of the subtotal words are then divided into two groups. Each group of bits is fed to a respective modulo 9 residue generator which calculates the modulo 9 residue of the group. The two resulting residues are then fed to a third modulo 9 residue generator which calculates the modulo 9 residue of the sum of the two residues, thereby providing the modulo 9 residue of the sum of the original set of data words. This result may then be compared in the conventional manner with the modulo 9 residue of the sum resulting from the addition operation to be checked.

    9.
    发明专利
    未知

    公开(公告)号：DE2720376A1

    公开(公告)日：1977-11-24

    申请号：DE2720376

    申请日：1977-05-06

    Applicant: IBM

    Inventor： CHEN TIEN CHI ,  ESWARAN KAPALI P ,  LUM VINCENT YU-SUN ,  TUNG CHIN

    IPC: G11C11/14 ,  G06F7/24 ,  G11C19/00 ,  G11C19/08 ,  G06F7/02

    Abstract: An apparatus for sorting of equal length records with the sorting time maximally overlapped by the time taken for loading and unloading of records. The minimal structure consists of a decision mechanism linked to and associated with a network of ladder structures. The activity within the network is so synchronized that the sorting activity in most ladders occurs while some ladder within the network is still undergoing the loading of input data; and during the unloading phase, the individually sorted data from each ladder are merged concurrently to produce a sequence of sorted records. The overlap between sorting and loading varies from 0 for records requiring no loading/unloading, to 100% for multi-ladder networks with loading/unloading.

Patent Agency Ranking