公开(公告)号：JPH065801A

公开(公告)日：1994-01-14

申请号：JP2876593

申请日：1993-02-18

Applicant: IBM

Inventor： AREKUSANDORU AKOBITSUKU ,  CHIN SHIAN SUU ,  MASHIYUU ROBAATO WAADOMAN ,  BEIN SON FUU

IPC: H01L27/105 ,  G11B17/028 ,  G11C14/00 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide one transistor non-volatile DRAM cell having two-layer floating gate to transfer content of a storage capacitor to the floating gate at the time of interrupting power. CONSTITUTION: A first layer of a floating gate is isolated from a storage node of a storage capacitor by a tunnel oxide, so that electrons can pass through a tunnel between the gate and the capacitor. A double electron injector is disposed between one layer floating gate and a storage node, so that the electrons can be injected between the floating gate and the storage gate. Further, an erasing gate for removing charge on the floating gate is realized. The erasing gate is isolated by a tunnel oxide or single electron injector structure, so that the electrons can move from the floating gate to the erasing gate.