公开(公告)号：JPH07297706A

公开(公告)日：1995-11-10

申请号：JP7024095

申请日：1995-03-28

Applicant: IBM

Inventor： SAN EICHI DON ,  KIRIHATA TOSHIAKI ,  MASHIYUU ROBAATO WAADOMAN

IPC: H03K17/687 ,  G05F3/24 ,  H03K19/0175

Abstract: PURPOSE: To limit a voltage difference between a source node and a gate node to a desired level by providing source and gate nodes to apply voltages and a control means for regulating the voltages to be applied to these nodes. CONSTITUTION: Another element consisting of the voltage driver of a pull-up NMOS transistor(Tr) QN1 is provided with an inverter INV1, PMOSTrs QP2, QP3 and QP4 and NMOSTrs QN5 and QN6. A node 24 is electrically connected with the input of an inverter INV3. The PMOSTrs QP2 and QP3 mutually operate and functionally form a diode 35. Then, this diode maintains the minimum voltage of a node 32 equal to a power supply voltage VDD, when the Tr QP2 is turned on. Further, the Tr QP3 is turned off because of the configuration of this diode 35, and the node 32 reaches a voltage higher than the voltage VDD because of the operation of a voltage-boosting part 23. As a result, the voltage difference between the gate and source of Tr QN1 is limited, and the service life of an off-chip driver 20 is prolonged.

公开(公告)号：JPH065801A

公开(公告)日：1994-01-14

申请号：JP2876593

申请日：1993-02-18

Applicant: IBM

Inventor： AREKUSANDORU AKOBITSUKU ,  CHIN SHIAN SUU ,  MASHIYUU ROBAATO WAADOMAN ,  BEIN SON FUU

IPC: H01L27/105 ,  G11B17/028 ,  G11C14/00 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide one transistor non-volatile DRAM cell having two-layer floating gate to transfer content of a storage capacitor to the floating gate at the time of interrupting power. CONSTITUTION: A first layer of a floating gate is isolated from a storage node of a storage capacitor by a tunnel oxide, so that electrons can pass through a tunnel between the gate and the capacitor. A double electron injector is disposed between one layer floating gate and a storage node, so that the electrons can be injected between the floating gate and the storage gate. Further, an erasing gate for removing charge on the floating gate is realized. The erasing gate is isolated by a tunnel oxide or single electron injector structure, so that the electrons can move from the floating gate to the erasing gate.