公开(公告)号：JPH0685281A

公开(公告)日：1994-03-25

申请号：JP230993

申请日：1993-01-11

Applicant: IBM

Inventor： TAKU HAN NIN ,  CHINNSHIYAN SUU

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide an improved EEPROM memory cell structure with a floating gate on a channel region where a selective injection part containing a high-dope region and a low-dope region along the direction of a channel width is located. CONSTITUTION: A cell contains a source region 16, a drain region 18, a floating gate 22, and a control gate 24. A channel region 20 below the floating gate 22 has both a highdope part 20-2 and a low-dope part 20-1. The manufacturing process of an EEPROM cell is also shown, thus achieving an efficient hot electron injection by a high-dope channel region while maintaining a high-read-out current by the low-dope channel region.