公开(公告)号：JPH03178133A

公开(公告)日：1991-08-02

申请号：JP29703390

申请日：1990-11-01

Applicant: IBM

Inventor： TEECHIYAN CHIEN ,  CHINNTE KENTO CHIYUAN ,  GUANNPIYON RI ,  TAKU HAN NIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

Abstract: PURPOSE: To prevent the punch-through of an edge or the breakdown from occurring by demarcating the base and emitter regions of a transistor, enabling one portion of a junction to be in parallel with at least a boundary surface, and providing a mesa-shaped p-n junction that ends at an insulating layer and where a polycrystalline region is electrically connected to the emitter region. CONSTITUTION: A p-n junction 5 of base-collector is formed at the boundary between a base 2 and a collector 4, and an oxide layer 6 partially covers the polycrystalline region of an extrinsic base 3, excluding a part that is directly connected to an intrinsic base 2. A silicon nitride layer 7 covers the oxide layer 6 and includes an extension part 8, and the edge part of the extension part demarcates the width of a base-emitter p-n junction 9. The p-n junction 9 is of mesa shape, the side part ends at the extension part 8 at one edge, and ends at the edge part of the flat part of the p-n junction 9 at the other edge, thus essentially eliminating punch-through or breakdown of the edge.

公开(公告)号：JPH0644571B2

公开(公告)日：1994-06-08

申请号：JP29703390

申请日：1990-11-01

Applicant: IBM

Inventor： TEECHIYAN CHIEN ,  CHINNTE KENTO CHIYUAN ,  GUANNPIYON RI ,  TAKU HAN NIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

公开(公告)号：JPH07176536A

公开(公告)日：1995-07-14

申请号：JP20023192

申请日：1992-07-02

Applicant: IBM

Inventor： TAKU HAN NIN

IPC: H01L21/331 ,  H01L21/74 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732

Abstract: PURPOSE: To provide a bipolar transistor that can be operated in a normal operation mode and an inverse operation mode. CONSTITUTION: A bipolar transistor has a thin sub-collector 22 that consists of the sandwich of a polycrystalline semiconductor material, silicide material, and polycrystalline semiconductor material arranged on an insulation layer 21. Since the sub-collector 22 is thin, the bipolar transistor 20 has a low influence to the phenomenon of alpha particles. Since a polycrystalline layer in contact with an inverse emitter exists, the current gain in inverse direction of the bipolar transistor 20 increases.

公开(公告)号：JPH0685281A

公开(公告)日：1994-03-25

申请号：JP230993

申请日：1993-01-11

Applicant: IBM

Inventor： TAKU HAN NIN ,  CHINNSHIYAN SUU

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide an improved EEPROM memory cell structure with a floating gate on a channel region where a selective injection part containing a high-dope region and a low-dope region along the direction of a channel width is located. CONSTITUTION: A cell contains a source region 16, a drain region 18, a floating gate 22, and a control gate 24. A channel region 20 below the floating gate 22 has both a highdope part 20-2 and a low-dope part 20-1. The manufacturing process of an EEPROM cell is also shown, thus achieving an efficient hot electron injection by a high-dope channel region while maintaining a high-read-out current by the low-dope channel region.