公开(公告)号：DE2538454A1

公开(公告)日：1976-04-15

申请号：DE2538454

申请日：1975-08-29

Applicant: IBM

Inventor： CHIRIONO OCTAVIO ISMAEL ,  HROMEK JOSEPH ,  JOSHI KAILASH CHANDRA ,  PHILLIPS JUN GEORGE CHARLES

IPC: H05K3/46 ,  B32B15/04 ,  C04B41/88 ,  H05K1/03 ,  H05K3/40 ,  H05K3/36

Abstract: This is a microelectronic multilayer circuit structure having circuit compatibility encapsulated within the circuit package including conductive electrical interconnection means formed by uniquely metallizing the "via" and/or blind interconnection holes within the circuit package. The assembly process provides means of uniformly metallizing the interlayer connecting holes.