公开(公告)号：DE2538454A1

公开(公告)日：1976-04-15

申请号：DE2538454

申请日：1975-08-29

Applicant: IBM

Inventor： CHIRIONO OCTAVIO ISMAEL ,  HROMEK JOSEPH ,  JOSHI KAILASH CHANDRA ,  PHILLIPS JUN GEORGE CHARLES

IPC: H05K3/46 ,  B32B15/04 ,  C04B41/88 ,  H05K1/03 ,  H05K3/40 ,  H05K3/36

Abstract: This is a microelectronic multilayer circuit structure having circuit compatibility encapsulated within the circuit package including conductive electrical interconnection means formed by uniquely metallizing the "via" and/or blind interconnection holes within the circuit package. The assembly process provides means of uniformly metallizing the interlayer connecting holes.

公开(公告)号：DE2960622D1

公开(公告)日：1981-11-12

申请号：DE2960622

申请日：1979-05-22

Applicant: IBM

Inventor： JOSHI KAILASH CHANDRA

IPC: G11C11/14 ,  G11C19/08 ,  G05F7/00

Abstract: Groups (11-13) of one or more magnetic domain chips (5) are mounted in an array on the circuitized surface (2) of a common substrate (1). A rectangular pattern of slots (14) is provided in the substrate (1) around each group (11-13). Each group is encompassed through the slots (14) by the turns of the inner and outer orthogonal solenoids (15-20) of its own exclusive rotational magnetic field drive system and by a permanent magnet bias field closed structure (22-32). Each chip (5) has a pattern of I/O pads (6) located on its under-surface (8). These pads (6) are bonded to a corresponding pattern of terminal pads (7) which are part of the circuitized surface (2) of the substrate (1). The interconnecting signal lines (9) to the terminal pads (7) of the substrate (1) pass through one or more of the four intersection corners formed between the slots (14) of the rectangular pattern. Preferably, the substrate (1) also accommodates integrated circuit modules and/or other components (34-41) mounted thereon which are associated with the drive, sense, and other support circuitry for the magnetic domain chips (5).

公开(公告)号：DE2223195A1

公开(公告)日：1973-01-11

申请号：DE2223195

申请日：1972-05-12

Applicant: IBM

Inventor： JOSHI KAILASH CHANDRA ,  KAPUR KISHEN NARAIN ,  MARTIN BYRON DALE ,  SHIPLEY JOHN FRANK

IPC: B23K1/018 ,  H01R9/16 ,  H05K13/04 ,  B23K5/20

公开(公告)号：DE2961573D1

公开(公告)日：1982-02-11

申请号：DE2961573

申请日：1979-02-23

Applicant: IBM

Inventor： JOSHI KAILASH CHANDRA ,  SPAIGHT RONALD NEIL

IPC: H05K3/34 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/485 ,  H01L23/522 ,  H01L23/538 ,  H01L27/04 ,  H01L39/00 ,  H01L23/48

Abstract: A plurality of metal studs are plated on a chip carrier surface in a pattern to match a terminal metal footprint on a chip to be joined. The studs are of sufficient height to permit flux cleaning, if necessary. After the studs are in place, the chip is aligned with the carrier and attached thereto, the chip pads containing a small amount of solder to provide the connecting joints. The carrier and chip are made of materials having nearly equal thermal expansion characteristics.

公开(公告)号：DE2748350A1

公开(公告)日：1978-05-11

申请号：DE2748350

申请日：1977-10-28

Applicant: IBM

Inventor： JOSHI KAILASH CHANDRA

IPC: H01L23/34 ,  H01L23/12 ,  H01L23/367 ,  H01L23/433 ,  H01L23/36

Abstract: Heat is removed from the silicon devices in an integrated circuit package by means of a stud which is slidably mounted in a cap enclosing the integrated circuit device. A low melt solder is used to join the stud to the cap and the same solder is also deposited on the stud tip, which will subsequently contact the integrated circuit device in the package. After the integrated circuit, substrate and cap are assembled and sealed, the assembly is heated to melt the low melt solder so that the stud slides down and makes contact with the integrated circuit device. A controlled pressure can be applied to the stud if sliding does not occur. Thereafter, the assembly is allowed to cool. Upon cooling, a submicron gap exists between the solder on the tip of the stud and the device providing electrical isolation, but not significantly degrading the thermal path between the device and the ambient atmosphere.

公开(公告)号：AU4245972A

公开(公告)日：1973-11-22

申请号：AU4245972

申请日：1972-05-18

Applicant: IBM

Inventor： JOSHI KAILASH CHANDRA ,  KAPUR KISHEN NARAIN ,  MARTIN BYRON DALE ,  SHIPLEY JOHN FRANK

IPC: B23K1/018 ,  H01R9/16 ,  H05K13/04 ,  B23K1/06