公开(公告)号：JPS57113485A

公开(公告)日：1982-07-14

申请号：JP18388481

申请日：1981-11-18

Applicant: IBM

Inventor： CHIYAN HON RAMU ,  GEIRII DAGURASU GURAISU ,  NINGU SHIYUU ,  HAWAADO REO KARUTAA

IPC: G11C14/00 ,  G11C11/34 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH06216378A

公开(公告)日：1994-08-05

申请号：JP31018593

申请日：1993-12-10

Applicant: IBM

Inventor： JIYON HAWAADO GIBUNZU ,  JIEEMUSU SUPAIROSU NEIKOSU ,  PIITAA OOSUCHIN BAAKU ,  KUREIGU MAASHIYARU HIRU ,  CHIYAN HON RAMU

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE: To improve sheet resistance of a gate of an integrated circuit device by charging an exposed part on a gate and a trench, extended on a junction part flat with a conductive material of different low sheet resistances. CONSTITUTION: A passivation layer 30 on a gate lamination 18 is removed, and the passivation layer 30 is removed to form a trench 36 to an insulation layer 32 and the gate lamination 18. A trench 40 is formed in an insulation layer on a junction part selectively with respect to a passivation layer, passes through the passivation layer 30 and extends selectively to a junction part 16. The trenches 36, 40 are charged with a conductive material 38 of different low sheet resistances to form a contact to the gate lamination 18 and the junction part 16, and are made flat together with the insulation layer 32. In this way, sheet resistance of a gate is improved.

公开(公告)号：JPH07193023A

公开(公告)日：1995-07-28

申请号：JP30296492

申请日：1992-10-14

Applicant: IBM

Inventor： CHIYAN HON RAMU ,  JIEROME BURETSUTO RASUKII ,  KUREIGU MAASHIYARU HIRU ,  JIEEMUSU SUPIROSU NAKOSU ,  SUTEIIBUN JIYON HOOMUZU ,  SUTEFUAN FURANKU GAISURAA ,  DEIBITSUDO KENEDEI ROODO

IPC: H01L21/28 ,  H01L21/223 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H01L29/43

Abstract: PURPOSE: To provide a semiconductor device where a trench is connected to a diffusion region, separated by dielectric and filled with polysilicon. CONSTITUTION: In this method, boron is lightly doped, and then a diffusion barrier layer 18, which prevents boron from diffusing into an upper polysilicon layer, is deposited when boron outer diffusing step is performed. Next, this barrier layer 18 is patterned and an opening is formed to make a contact. Next, an intrinsic polysilicon layer is deposited on the barrier layer 18 and in the contact opening by using low pressure chemical vapor deposition. Next, boron is diffused into the polysilicon layer by annealing. Next, the polysilicon layer where boron is not diffused is removed by preferential etching, and polysilicon strap which is connected to a trench 12 and a diffusive region 10 is left. Subsequently, this remaining polysilicon strap 34 is oxidized for protecting this polysilicon strap 34 from silicide formed during the next process.

公开(公告)号：JPH05198779A

公开(公告)日：1993-08-06

申请号：JP19247092

申请日：1992-07-20

Applicant: IBM

Inventor： BURUUSU ARAN KAUFUMAN ,  CHIYAN HON RAMU ,  JIEROOMU BURETSUTO RASUKII

IPC: G11C17/00 ,  B82B1/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a memory cell which is suitable for programmable read only memory that is provided with cell direct writing capability and can be erased electrically. CONSTITUTION: A memory cell 10 is formed on a substrate 12 and uses as inversion source gate 18 arranged on the substrate, so as to generated a depletion source 20. The depletion source 20 forms channel areas L1 and L2 on the substrate, together with a related drain 14. An electrically isolated floating gate 26 is arranged on the substrate, and it covers at least one area L1 of the channel regions. A program gate 30 is arranged so as to overlap the floating gate, and an access gate 34 is formed being aligned with the channel region at least in part, so that a double gate device may be formed. An array of memory cell is also disclosed.