公开(公告)号：JPH02294990A

公开(公告)日：1990-12-05

申请号：JP10324590

申请日：1990-04-20

Applicant: IBM

Inventor： JIYON ATOKINSON FUIFUIIRUDO ,  HAWAADO REO KARUTAA

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097

Abstract: PURPOSE: To improve the data signal/noise ratio in a high density DRAM by using a non-selective bit line as an AC ground bus and shielding a detected data bit line or a column line. CONSTITUTION: An isolation clock ISOA lowers and turns off an isolation device 1 and 2, at the beginning of an access cycle, in the case of access to a memory cell responding to a word line ML situated on the left side of a sense amplifier 10 on a bit line BL2. With ISOA lowering, a P channel/clamp device 9, 11 turns on, connecting to an array power source potential VD3 a non-active bit line segment BL1 and BL1' separated from the amplifier 10. When a reference word line R2' corresponding to the selected line ML becomes an active state, data and a reference signal are connected to a line segment BL2 and BL2'. Accordingly, signals generating on the reference bit line and the data bit line are all shielded from all dynamic interline connections.

公开(公告)号：JPH02278355A

公开(公告)日：1990-11-14

申请号：JP5682490

申请日：1990-03-09

Applicant: IBM

Inventor： ROBAATO MAACHIN BUREIKU ,  DAGURASU KUREIGU BOOSEN ,  CHINNRONGU CHIEN ,  JIYON ATOKINSON FUIFUIIRUDO ,  HAWAADO REO KARUTAA

IPC: G06F12/16 ,  G06F11/10

Abstract: PURPOSE: To solve the confrontation which can exist between an error correcting system at a chip level and that at a system level by providing an error correction and detection means at not less than two levels so as to prohibit the operation of an error correction and detection means at a lower-order level when a multiplex fault is generated. CONSTITUTION: A correction impossible error detection signal from the syndrome generator 91 for a chip level error correction circuit 90 is supplied for a latch 55 through an AND gate 53 and an OR gate 56, and the latch 5 supplies a correction prohibiting signal to a decoder 92. The reset input R of he latch 55 receives a reset mode A or B signal generated similarly to a set mode A signal. After a system error circuit is attained, the reset mode A signal resets only he latch 55 through the OR gate 54 to recover normal operation. A set mode B signal is used for executing system judgment by prohibiting on-ship error correction for attaching the memory bit mapping of the position of defective data. Thereby the fault tolerant ability of a high density semiconductor memory is improved.

公开(公告)号：JPS57105888A

公开(公告)日：1982-07-01

申请号：JP13987681

申请日：1981-09-07

Applicant: IBM

Inventor： HAWAADO REO KARUTAA ,  HARITSUSHIYU NARANDASU KOOTETS ,  PARUSOTAMU TORIKAMU PATERU

IPC: H01L27/112 ,  G11C14/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH06223599A

公开(公告)日：1994-08-12

申请号：JP13864593

申请日：1993-06-10

Applicant: IBM

Inventor： JIYON EDOWAADO BAASU ,  HAWAADO REO KARUTAA

IPC: G11C11/401 ,  G11C7/20 ,  G11C8/12 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/50

Abstract: PURPOSE: To attain batch writing in the plural memory cells of a memory device such as a DRAM for the purpose of a test and stress impression. CONSTITUTION: The first set of word lines (W1 and W3) which control the connection of the memory cells of the first set of memory cells with the first bit line of each bit line pair (39T and 39C) are turned on. Afterwards, a voltage between the two bit lines of the bit line pair is averaged (24), and the charge of the first bit line of the bit line pair is made higher than the charge of the second bit line of the bit line pair. Next, a sense amplifier (23) connected with the bit line pair is turned on, the difference of the charges between the bit line pair is sensed, and the first set of memory cells are charged. Then, the second set of word lines (W0 and W2) which control the connection of the memory cells of the second set of memory cells with the second bit line are turned on. At last, the previously turned-on word lines are turned off, and then the sense amplifier is turned off.

公开(公告)号：JPH0613583A

公开(公告)日：1994-01-21

申请号：JP3189093

申请日：1993-02-22

Applicant: IBM

Inventor： ARUBAATO SUTEIIBUN BERUGENDAAR ,  KUROODO RUI BERUTAN ,  JIYON EDOWAADO KUROONIN ,  HAWAADO REO KARUTAA ,  DONARUDO MAKARUPAIN KENII ,  CHIYUN HON RAMU ,  SHIN SAN RII

IPC: H01L27/10 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a shadow RAM, which occupies only 120% or less of the space of only a DRAM by using an EEPROM in a trench in the array of the DRAM. CONSTITUTION: A memory capacitor 3 of the deep trench of polysilicon is arranged between a word line 1 and a bit line, where its contact 2 is shown. An insulating region 4 of a shallow trench is located between a pair of the deep-trench memory capacitors 3 neighboring the contact 2 and blocks stray surface currents. An EEPROM trench includes a series of discontinuous polysilicon floating gates 5, a continuous polysilicon recall-gate extending part 6, a continuous polysilicon program gate, a silicon oxide layer 8 for insulation and a dielectric spacer 7 having abundant silicon between the floating gate 5 and the recall-gate extending part 6, and between the floating gate and the program gate.

公开(公告)号：JPH05198173A

公开(公告)日：1993-08-06

申请号：JP1690091

申请日：1991-01-18

Applicant: IBM

Inventor： JIYON EDOWAADO BAASU JIYUNIA ,  CHIYAARUSU EDOWAADO DOREIKU ,  UIRIAMU POORU HOOBISU ,  HAWAADO REO KARUTAA ,  GOODON AASAA KERII JIYUNIA ,  SUKOTSUTO KURARENSU RUISU ,  DANIERU JIYON NITSUKERU ,  JIEEMUSU ANDORIYU YANKOSUKII

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406

Abstract: PURPOSE: To reduce power for a dynamic random access memory using plural modules. CONSTITUTION: The memory includes plural memory arrays 26 to 40, the word line of each memory array is selected by related 1/512 decoding circuits 42 to 56, and the bit/sense line of each memory array is selected by related 1/1024 decoding circuits 68 to 82. The 1/512 decoding circuits 42 to 56 are selectively operated by transmission gate devices 58 to 64, which are selectively operated by a 1/4 decoding circuit 66. The 1/1024 decoding circuits 68 to 82 are selectively operated by transmission gate devices 84 to 90.

公开(公告)号：JPS58222620A

公开(公告)日：1983-12-24

申请号：JP6851583

申请日：1983-04-20

Applicant: Ibm

Inventor： HAWAADO REO KARUTAA ,  FURANSHISU UORUTAA UIIDOMAN

IPC: G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  H03K19/096 ,  H03K19/177

CPC classification number: G06F7/5057 ,  H03K19/096 ,  H03K19/1772

公开(公告)号：JPH09106968A

公开(公告)日：1997-04-22

申请号：JP17785096

申请日：1996-07-08

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  UEIN JIYON HAUERU ,  HAWAADO REO KARUTAA ,  PATORISHIA EREN MARUMIRION ,  ANSONII MAIKERU PARAGONIA ,  BAANADETSUTO AN PIASON ,  DENISU AASAA SHIYUMITSUTO

IPC: H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065

Abstract: PROBLEM TO BE SOLVED: To demarcate the edge of an IC chip accurately at water-level manufacturing by forming first trenches into a wafer by lithography, polishing the main plane of the IC chip towards the bottom sections of the first trenches and thinning the IC chip. SOLUTION: First trenches 25 crossing the first main plane of a water 11 and having bottom sections are formed into the wafer 11 by lithography. The second main plane of an IC chip is polished towards the bottoms of the first trenches 25 and towards the first main plane of the wafer 11 so that the first trenches 25 demarcate at least one edge of the IC chip, and the IC chip is thinned. The first trenches 25 are filled with an insulation material 35, a transfer metallic layer 39 is formed onto the first main plane of the wafer, and second trenches 45 coinciding with the first trenches 25 are formed, and the layer 39 is polished.

公开(公告)号：JPH0917753A

公开(公告)日：1997-01-17

申请号：JP13619296

申请日：1996-05-30

Applicant: IBM

Inventor： EICHI BAANHAADO POTSUGU ,  YOHAN GURESHIYUNAA ,  HAWAADO REO KARUTAA ,  REIMONDO JIEEMUZU ROSUNAA

IPC: H01L21/28 ,  H01L21/301 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor die unit whose dimensions are precise. SOLUTION: A semiconductor die unit 150 to be provided contains a first semiconductor substrate which comprises a first face and a second generally opposite face and in which a plurality of semiconductor devices are formed. The semiconductor die unit to be provided contains at least one of a first metal coating layer which is arranged on a first face of the first semiconductor substrate in order to form interconnections 414 between the semiconductor devices. The outside dimensions of the semiconductor die unit are partitioned by lithography. A carrier 208 which supports the semiconductor die unit contains a substrate comprising a recess partitioned by lithography in order to receive the semiconductor die unit.

公开(公告)号：JPH06204832A

公开(公告)日：1994-07-22

申请号：JP24861693

申请日：1993-09-10

Applicant: IBM

Inventor： SURIDA DEIBAKARUNI ,  JIEFURI HARISU DORAIBERUBISU ,  UEIN FUREDERITSUKU ERISU ,  ANATOORU FUAAMAN ,  HAWAADO REO KARUTAA

IPC: H01L27/00 ,  H03K17/22

Abstract: PURPOSE: To make the detection of an on-chip voltage during the gradient rise of power supply possible within a high reliability range by utilizing an auxiliary threshold current, so that sufficient power supply detection may be performed during the gradient rise of the power supply, when the voltage rises. CONSTITUTION: An auxiliary threshold current has a characteristic such that it varies depending upon the length of the transistor of a device or the device itself when the device is short. However, the variability of the characteristic is reduced, when the device is long. Therefore, the sensitivity of a power supply rise detecting circuit with respect to a slow power supply gradient can be eliminated by utilizing the auxiliary threshold currents of devices connected to a latch L and having various lengths. The charging of a latch node is controlled by the auxiliary threshold current, and a latched-state threshold voltage is mainly decided by the device widths of a P-type channel field effect transistor P0 and an N-type channel field effect transistor N0. In this case, the use of the latch L is meaningful, because the latch L provides an abrupt status change during the slow power supply gradient for avoiding oscillation in a circuit which is intended to be initialized.