公开(公告)号：JPH0661493A

公开(公告)日：1994-03-04

申请号：JP13053693

申请日：1993-06-01

Applicant: IBM

Inventor： CHIYANNMIN SHII ,  RUISU ERUUSHII SHIYUU ,  SEIKI OGURA

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE: To provide a field-effect transistor(FET) having a vertical gate and a very thin channel sandwiched between a source layer and a drain layer. CONSTITUTION: An FET is formed on a silicon-on-insulator(SOI) substrate having an Si layer 12 acting as a first layer, e.g. source layer. A very thin channel 22 (e.g. of 0.1 μm) is formed by a low temp. epitaxial(LTE) process. A chemical vapor deposition polysilicon layer 28 forms a top layer (e.g. drain layer). An opening is etched through the three layers down to an insulation substrate and the opening wall is oxidized to form a gate oxide layer 33. Polysilicon fills the openings and is deposited to form a vertical gate 34.