公开(公告)号：MY104983A

公开(公告)日：1994-07-30

申请号：MYPI19891036

申请日：1989-07-31

Applicant: IBM

Inventor： SHAH AKBAR ,  PATRICIA LAVELLE KROESEN ,  SEIKI OGURA ,  NIVO ROVEDO

IPC: H01L29/72 ,  G03C3/00 ,  H01L29/73 ,  H01L21/28 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: THE BIPOLAR TRANSISTOR (10) COMPRISES OF A COLLECTOR LAYER (12); A BASE LAYER (14); AN EMITTER LAYER; A FIRST SIDEWALL INSULATING LAYER (18) DISPOSED ADJACENT TO AND IN CONTACT WITH ONE SIDE OF THE EMITTER LAYER (16), THE BASE LAYER (14), AND AT LEAST A PORTION OF THE COLLECTOR LAYER (12); A SECOND SIDEWALL INSULATING LAYER (20) AND A BASE CONTACT EXTENSION LAYER (22) FORMED FROM HEAVILY DOPED SEMICONDUCTOR MATERIAL OF THE SAME CONDUCTIVITY TYPE AS THE BASE LAYER (14), SAID BASE CONTACT EXTENSION LAYER (22) BEING IN CONTACT WITH AN EXTENDING LATERALLY FROM ANOTHER SIDE OF THE BASE LAYER (14). THE STRUCTURE FURTHER INCLUDES A BASE CONTACT INTERCONNECT (24), A COLLECTOR CONTACT EXTENSION LAYER (26) FORMED FROM DOPED SEMICONDUCTOR MATERIAL WITH THE SAME CONDUCTIVITY TYPE AS THE COLLECTOR LAYER (12),WITH THE COLLECTOR CONTACT EXTENSION LAYER (26) BEING IN CONTACT WITH THE COLLECTOR LAYER AND EXTENDING LATERALLY FROM OR BELOW THE ONE SIDE THEREOF; AND A COLLECTOR CONTACT INTERCONNECT.(FIG. 8)

公开(公告)号：JPS6155973A

公开(公告)日：1986-03-20

申请号：JP8151585

申请日：1985-04-18

Applicant: Ibm

Inventor： KURISUTOFUAA FURANKU KOODERA ,  SEIKI OGURA

IPC: H01L21/265 ,  H01L21/338 ,  H01L29/08 ,  H01L29/10 ,  H01L29/812

CPC classification number: H01L29/66878 ,  H01L29/0891 ,  H01L29/1075 ,  H01L29/812 ,  Y10S257/90

公开(公告)号：JPH04180673A

公开(公告)日：1992-06-26

申请号：JP25546090

申请日：1990-09-27

Applicant: IBM

Inventor： SEIKI OGURA ,  POORU JIEI TSUANGU

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

Abstract: PURPOSE: To easily manufacture a high capacity memory cell by injecting a P type impurity between a gate electrode and an insulation body area adjacent to it, performing reactive ion etching, then ion-injecting an N type impurity and forming a capacitor electrode. CONSTITUTION: After forming an SiO2 layer 14 around a polysilicon gate electrode, an insulation body layer 16 is formed. Then, the layer 16 is directionally reactively ion-etched and removed leaving a side wall spacer 20. Then, capacitor plate oxide is grown on an area 25, a blocking resist mask is applied and the P type impurity is injected. Then, the mask is removed and the N type impurity is injected and annealed. Then, polysilicon is stuck and a capacitor plate 30 is formed. Thus, the contour of less than 1μm is realized by using optical lithography and a fast dynamic RAM is easily manufactured.

公开(公告)号：JPS62219943A

公开(公告)日：1987-09-28

申请号：JP200787

申请日：1987-01-09

Applicant: IBM

Inventor： ANSONII JIYON DARI ,  SEIKI OGURA ,  YAKOBU RAIZUMAN ,  NIBUO ROBUDO

IPC: H01L21/76 ,  H01L21/762

公开(公告)号：JPS60124967A

公开(公告)日：1985-07-04

申请号：JP23342884

申请日：1984-11-07

Applicant: IBM

Inventor： SEIKI OGURA ,  YAKOBU RAIZUMAN ,  NIBUO ROBUDO ,  JIYOSEFU FURANSHISU SHIEPAADO

IPC: H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73

公开(公告)号：JPH07202013A

公开(公告)日：1995-08-04

申请号：JP29623294

申请日：1994-11-30

Applicant: IBM

Inventor： RUISU RUUCHIEN SU ,  JIYOSEFU FURANSHISU SHIEPAADO ,  SEIKI OGURA

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/762 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

Abstract: PURPOSE: To achieve the smallest horizontal size, without losing insulation effects by forming an insulating sidewall in an opening for an insulating body, and isolating a gate contact terminal from each contact terminal of a source and a drain. CONSTITUTION: A gate stack is constituted of a gate oxide layer 102, a polysilicon layer 110 and a nitride layer 120, and the doping of the polysilicon layer is carried out, and an interposed layer 124 is formed as an oxide layer as an etch stop material, and an opening is opened to the gate laminate in a region which is a field insulating part. Then, the opening is stopped on the oxide layer 102, and a sidewall formed at the side part insulates the gate stack from a strap connection working as a mask for implant of a source or a drain. Then, when the polysilicon layer is deposited in the opening and the nitride layer 120 is removed, an insulating layer 113 for protecting a polysilicon contact terminal 115 is grown, a gate 110 is exposed, and a gate contact terminal 112 is provided. Thus, a smallest horizontal size can be achieved, without losing insulation effects.

公开(公告)号：JPH06204495A

公开(公告)日：1994-07-22

申请号：JP24664793

申请日：1993-10-01

Applicant: IBM

Inventor： RUISU RUCHIEN HIYUU ,  CHIYANMIN HII ,  SEIKI OGURA

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide an improved cell of an electrically erasable programmable flush memory dedicated to read out to be used for a memory cell. CONSTITUTION: This electrically erasable programmable flash memory dedicated to read out is composed of a data housing floating gate 130 and a dual gate transistor consisting of a selective gate 120 by which a cell is accessed. Gates 120 and 130 are formed by a polycrystalline silicon side wall, and the gates 120 and 130 are separated by a thin vertical oxide film member 231 which is formed by growing an oxide film on the vertical polycrystalline silicon side having a hole. Accordingly, as the floating gate 130 and the selective gate 120 form a side wall, they can be formed in the size smaller than that obtained by optical lithography, and they are not restricted by the dimensions obtained by optical lithography.

公开(公告)号：JPH0653435A

公开(公告)日：1994-02-25

申请号：JP12181493

申请日：1993-05-25

Applicant: IBM

Inventor： CHIYANNMIN SHIIFU ,  RUISU ERU SHII SHIYUU ,  SEIKI OGURA

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To provide a high-density DRAM cell array which is composed of a common-gate double-bit array, allowing conventional photolithographic process to be used. CONSTITUTION: A high-density DRAM cell array has very short-channel vertical gate transfer transistors, which can be made by the conventional photolithographic process. The DRAM array is composed of a common-gate double-bit array. Trench storage capacitors and vertical FETs face opposite common vertical gates and common substrate and can share bits and substrate contact through adjacent cells.

公开(公告)号：JPH04276653A

公开(公告)日：1992-10-01

申请号：JP35108891

申请日：1991-12-11

Applicant: IBM

Inventor： MAIKERU MONKOUSUKI ,  SEIKI OGURA ,  NIBUO ROBUEDO ,  JIYOZEFU FURANSHISU SHIEPAADO

IPC: H01L27/06 ,  H01L21/225 ,  H01L21/763 ,  H01L21/8249

Abstract: PURPOSE: To easily assemble an integrated circuit device which uses circuit elements on the same chip by different technologies. CONSTITUTION: This process includes a state for forming part of a circuit element at the same time by both CMOS and bipolar technologies, a stage for making the circuit element by to the bipolar technology and partially completing the circuit element by the CMOS technology, a stage for masking the circuit element by the CMOS technology and completing the circuit element by the bipolar technology, and a stage for completing the circuit element by the CMOS technology. A self-aligning and self-making process is used at a maximum and several stages are performed at the same time for devices of different technologies to decrease the number of stages. Further, making stage in use has allowance for a position shift, so the manufacture yield becomes high.

公开(公告)号：JPH0254934A

公开(公告)日：1990-02-23

申请号：JP14977489

申请日：1989-06-14

Applicant: IBM

Inventor： SHIYAA AAKUBAA ,  PATORISHIA RABERII KUROOSEN ,  SEIKI OGURA ,  NIIIBO ROBEDO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: PURPOSE: To make a contact for reaching a subcollector needles so as to increase an operation speed by making a base contact expansion layer laterally contact a base layer and making a collector contact expanding layer to contact the base of a collector layer. CONSTITUTION: An FET 10 is provided with a collector layer 12, a base layer 14 and an emitter layer 16 besides including a sidewall insulator layer 18 arranged near and in contact with one side of one part each of the respective layers, also including a sidewall insulating layer 20 arranged near and in contact with other side of one part each of the layers 16, 14. Further, FET 10 is in contact with the other side of the layer 14 and being laterally extended and including a base contact extension layer 22 formed of a semiconductor material in the same conductive form with the layer 14 and being densely doped and the base contact interconnection 24 is arranged on the upper part surface 62 of the layer 22 being separated form the layer 16. A collector contact extension layer 26 is in contact with the layer 12 being laterally extended from one side of the layer 12. Then, the layer 26 is in contact with the base of the layer 12 being laterally extended.