公开(公告)号：SG83184A1

公开(公告)日：2001-09-18

申请号：SG200000422

申请日：2000-01-22

Applicant: IBM

Inventor： CHUNG HON LAM ,  GLEN L MILES ,  JAMES SPIROS NAKOS ,  CHRISTA R WILLETS

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.