公开(公告)号：GB2573450A

公开(公告)日：2019-11-06

申请号：GB201910103

申请日：2018-01-09

Applicant: IBM

Inventor： WANKI KIM ,  CHUNG HON LAM ,  ROBERT BRUCE ,  FABIO CARTA

IPC: H01L45/00 ,  H01L21/82 ,  H01L27/24

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

公开(公告)号：GB2573450B

公开(公告)日：2021-10-06

申请号：GB201910103

申请日：2018-01-09

Applicant: IBM

Inventor： WANKI KIM ,  CHUNG HON LAM ,  ROBERT BRUCE ,  FABIO CARTA

IPC: H01L45/00 ,  H01L21/82 ,  H01L27/24

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

公开(公告)号：GB2487636B

公开(公告)日：2016-08-17

申请号：GB201200716

申请日：2010-08-25

Applicant: IBM

Inventor： MATTHEW JOSEPH BREITWISCH ,  CHUNG HON LAM ,  BIPIN RAJENDRAN ,  DHARMENDRA SHANTILAL MODHA

IPC: G06N3/063 ,  G11C11/54 ,  H01L27/28

公开(公告)号：SG83184A1

公开(公告)日：2001-09-18

申请号：SG200000422

申请日：2000-01-22

Applicant: IBM

Inventor： CHUNG HON LAM ,  GLEN L MILES ,  JAMES SPIROS NAKOS ,  CHRISTA R WILLETS

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.