公开(公告)号：GB2579534B

公开(公告)日：2020-12-16

申请号：GB202006338

申请日：2018-10-03

Applicant: IBM

Inventor： BALARAM SINHAROY ,  BRYAN LLOYD ,  CHRISTOPHER GONZALES

IPC: G06F9/38 ,  G06F9/318

Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of- order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

公开(公告)号：GB2579534A

公开(公告)日：2020-06-24

申请号：GB202006338

申请日：2018-10-03

Applicant: IBM

Inventor： BALARAM SINHAROY ,  BRYAN LLOYD ,  CHRISTOPHER GONZALES

IPC: G06F9/38 ,  G06F9/318

Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.