公开(公告)号：JP2007172610A

公开(公告)日：2007-07-05

申请号：JP2006337623

申请日：2006-12-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SATYA P SHARMA ,  BRUCE G MEALEY ,  BALARAM SINHAROY ,  PETER H HOCHSCHILD ,  RAVI K ARIMILLI ,  RAMA K GOVINDARAJU

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38

CPC classification number: G06F12/1441 ,  G06F12/0888 ,  G06F12/0897

Abstract: PROBLEM TO BE SOLVED: To protect a content of a memory page in execution of a semi-synchronous memory copy instruction. SOLUTION: A method of protecting the content of the memory page in a superscalar processor includes determining a start of a semi-synchronous memory copy operation. An address range of executing the semi-synchronous memory copy operation is determined therein. An issued instruction removing a page table entry is detected. The method further includes determining whether the page table entry associated with at least one address within an address range is destined to be removed in the issued instruction, or not. The execution of the issued instruction is stopped until the semi-synchronous memory copy operation is finished, in response to the issued instruction being destined to remove the page entry. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：在执行半同步存储器复制指令时保护存储器页的内容。 解决方案：在超标量处理器中保护存储器页面的内容的方法包括确定半同步存储器复制操作的开始。 确定执行半同步存储器复制操作的地址范围。 检测到发出的删除页表条目的指令。 该方法还包括确定与地址范围内的至少一个地址相关联的页表条目是否注定在已发出的指令中被移除。 所发出的指令的执行停止，直到半同步存储器复制操作完成为止，响应于发出的指令旨在去除页面条目。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007172609A

公开(公告)日：2007-07-05

申请号：JP2006337593

申请日：2006-12-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SATYA P SHARMA ,  BRUCE G MEALEY ,  BALARAM SINHAROY ,  PETER H HOCHSCHILD ,  RAVI K ARIMILLI ,  RAMA K GOVINDARAJU

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/02 ,  G06F12/04 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/3824

Abstract: PROBLEM TO BE SOLVED: To provide a memory copy operation wherein a processor continuously executes subsequent commands during the memory copy operation, and to avoid an unnecessary processor downtime.
SOLUTION: A method for semi-synchronously copying data from a first portion of a memory to a second portion of a memory comprises a step of receiving, in a processor, a memory copy instruction for a semi-synchronous memory copy operation preserving temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit, the memory copy instruction including at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied; a step of placing the memory copy instruction in queues 232, 234, and 236 coupled to the memory controller for execution by a memory controller 208; and a step of continuing at least one subsequent instruction to be executed as the subsequent instruction becomes available from an instruction pipeline.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供存储器复制操作，其中处理器在存储器复制操作期间连续执行后续命令，并且避免不必要的处理器停机。 解决方案：一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的方法，包括在处理器中接收用于保持半同步存储器复制操作的存储器复制指令的步骤 通过设置标志位，对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性，所述存储器复制指令至少包括虚拟源地址，虚拟源 目标地址和标识要复制的字节数的指示符; 将存储器复制指令置于耦合到存储器控制器的队列232,234和236中以便由存储器控制器208执行的步骤; 以及随着随后的指令从指令流水线变得可用，继续执行待执行的至少一个后续指令的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：BRPI0409710B1

公开(公告)日：2020-01-14

申请号：BRPI0409710

申请日：2004-04-14

Applicant: IBM

Inventor： BALARAM SINHAROY ,  LARRY SCOTT LEITNER ,  MICHAEL STEPHEN FLOYD ,  RONALD NICK KALLA ,  WILLIAM JOSEPH ARMSTRONG

IPC: G06F9/38 ,  G06F11/34

Abstract: "método e lógica contábil para determinar a utilização de recurso de processador per-thread em um processador de múltiplos threads simultâneos (smt)". um método contábil e lógica para determinar utilização de recurso de processador por-thread em um processador de múltiplos threads (smt) provê um mecanismo para contabilizar o uso do recurso de processador por programas e threads dentro de programas. o uso de recurso relativo é determinado pela detecção de despacho de instruções para múltiplos thread ativos dentro do processador, que podem incluir threads ociosos que ainda estão ocupando recursos do processador. se instruções são despachadas para todos os threads ou nenhum thread, o ciclo de processador é contabilizado igualmente para todos os threads. alternativamente, se nenhum thread está no estado de despacho, a contabilização pode ser feita usando um estado anterior ou em conformidade com taxas de níveis de prioridade de threads. se apenas um thread é despachado, aquele thread é contabilizado pelo ciclo de processador completo. se múltiplos threads são despachados, mas menos que todos os threads são despachados (em um processador suportando mais que dois threads), o ciclo de processador é faturado uniformemente pelos threads despachados. múltiplos threads podem ser detectados para os threads e um uso de recurso fracionado para cada thread e os contadores podem ser atualizados de acordo com os seus usos fracionados.

公开(公告)号：GB2581460B

公开(公告)日：2021-01-06

申请号：GB202009111

申请日：2018-11-09

Applicant: IBM

Inventor： JOEL SILBERMAN ,  BALARAM SINHAROY

IPC: G06F9/38

Abstract: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

公开(公告)号：GB2581460A

公开(公告)日：2020-08-19

申请号：GB202009111

申请日：2018-11-09

Applicant: IBM

Inventor： JOEL SILBERMAN ,  BALARAM SINHAROY

IPC: G06F9/38

Abstract: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

公开(公告)号：GB2579534B

公开(公告)日：2020-12-16

申请号：GB202006338

申请日：2018-10-03

Applicant: IBM

Inventor： BALARAM SINHAROY ,  BRYAN LLOYD ,  CHRISTOPHER GONZALES

IPC: G06F9/38 ,  G06F9/318

Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of- order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

公开(公告)号：GB2581945A

公开(公告)日：2020-09-02

申请号：GB202009499

申请日：2018-11-09

Applicant: IBM

Inventor： JOEL SILBERMAN ,  BALARAM SINHAROY

IPC: G06F9/38

Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked. Instructions are issued from the issue queue based at least in part on the tracking.

公开(公告)号：GB2579534A

公开(公告)日：2020-06-24

申请号：GB202006338

申请日：2018-10-03

Applicant: IBM

Inventor： BALARAM SINHAROY ,  BRYAN LLOYD ,  CHRISTOPHER GONZALES

IPC: G06F9/38 ,  G06F9/318

Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.

公开(公告)号：GB2581945B

公开(公告)日：2021-01-20

申请号：GB202009499

申请日：2018-11-09

Applicant: IBM

Inventor： JOEL SILBERMAN ,  BALARAM SINHAROY

IPC: G06F9/38

Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked. Instructions are issued from the issue queue based at least in part on the tracking.

公开(公告)号：GB2581759B

公开(公告)日：2021-01-20

申请号：GB202009231

申请日：2018-11-09

Applicant: IBM

Inventor： JOEL SILBERMAN ,  BALARAM SINHAROY

IPC: G06F9/38

Abstract: Aspects of the invention include detecting, in an out-of-order (OoO) processor, that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is the oldest group in an entry of a global completion table (GCT). It is determined that the entry in the GCT is a merged entry that is associated with both the first group of in-flight instructions and a second group of in-flight instructions dispatched immediately subsequent to the first group of in-flight instructions. The first group of in-flight instructions and the second group of in-flight instructions are completed in a single processor cycle. The completing is based at least in part on detecting that all instructions in the first group of in-flight instructions have a status of finished. The completing includes requesting release of resources utilized by both the first and second groups of in-flight instructions.