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    FET LOAD GATE COMPENSATOR
    2.
    发明专利
    FET LOAD GATE COMPENSATOR 未知

    公开(公告)号：CA1042520A

    公开(公告)日：1978-11-14

    申请号：CA236362

    申请日：1975-09-25

    Applicant: IBM

    Inventor： CHU WILLIAM M ,  LEE JAMES M

    IPC: H03K5/04 ,  H02M3/07 ,  H02M3/155 ,  H03K3/356 ,  H03K5/13 ,  H03K5/15 ,  H03K17/14 ,  H03K17/28 ,  H03K17/687 ,  H03K19/003 ,  H03K19/096 ,  H03K1/17

    Abstract: FET LOAD GATE COMPENSATOR An FET load gate compensator employing feedback to control the load gate voltage holds the circuit delay and power dissipation of an integrated circuit nearly constant. The integrated circuit chip is provided with several stages of inverters which act as a delay sensor to simulate the delay of the operational circuit on the chip. The time delay of the delay sensor on the integrated circuit chip is compared with an external clock reference by a delay comparator. The delay comparator generates an output voltage which is used to adjust the load gate voltage until the delay in the delay sensor is equal to the clock reference. Since the same load gate voltage is distributed in the rest of the operational circuits in the integrated circuit chip, the delay times of these circuits will track with that of the delay sensor and thus also tend to be held constant.

    4.
    发明专利
    未知

    公开(公告)号：FR2276661A1

    公开(公告)日：1976-01-23

    申请号：FR7516532

    申请日：1975-05-21

    Applicant: IBM

    Inventor： CHU WILLIAM M ,  SONODA GEORGE

    IPC: G11C11/413 ,  G06F11/22 ,  G11C11/412 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/50 ,  G11C29/56

    Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.

    5.
    发明专利
    未知

    公开(公告)号：DE2527486A1

    公开(公告)日：1976-01-15

    申请号：DE2527486

    申请日：1975-06-20

    Applicant: IBM

    Inventor： CHU WILLIAM M ,  SONODA GEORGE

    IPC: G11C11/413 ,  G06F11/22 ,  G11C11/412 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/50 ,  G11C29/56 ,  G11C7/00

    Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.

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