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    Regenerative fet source follower
    1.
    发明授权
    Regenerative fet source follower 失效
    再生FET源头

    公开(公告)号：US3564290A

    公开(公告)日：1971-02-16

    申请号：US3564290D

    申请日：1969-03-13

    Applicant: IBM

    Inventor： SONODA GEORGE

    IPC: H03K19/096 ,  H03K17/60

    CPC classification number: H03K19/096

    Abstract: This specification describes a logic circuit having a capacitor coupled between the gate and source of an FET to cause the potential at the gate to follow the potential at source. The charge of this capacitor is controlled to render the FET conductive or nonconductive so that pulses applied to the drain of the FET can be selectively gated or not gated through the FET to a load connected to the source of the FET. By operating the FET in this way small supply voltages may be used. These voltages can be in the order of the size of the signals transmitted to the load.

    4.
    发明专利
    未知

    公开(公告)号：DE2621654A1

    公开(公告)日：1977-01-20

    申请号：DE2621654

    申请日：1976-05-15

    Applicant: IBM

    Inventor： SONODA GEORGE

    IPC: G11C11/412 ,  G11C7/00 ,  G11C11/40

    Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. The load devices are never fully turned off so that complete D.C. stability is achieved with a four device cell because no one cell in an array of memory cells ever goes into a data retention mode.

    6.
    发明专利
    未知

    公开(公告)号：FR2296244A1

    公开(公告)日：1976-07-23

    申请号：FR7535239

    申请日：1975-11-10

    Applicant: IBM

    Inventor： SONODA GEORGE

    IPC: G11C11/412 ,  G11C11/40

    Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

    D.C. STABLE SEMICONDUCTOR MEMORY CELL
    9.
    发明专利
    D.C. STABLE SEMICONDUCTOR MEMORY CELL 未知

    公开(公告)号：CA1060994A

    公开(公告)日：1979-08-21

    申请号：CA237271

    申请日：1975-10-08

    Applicant: IBM

    Inventor： ASKIN HALUK O ,  JACOBSON EDWARD C ,  LEE JAMES M ,  SONODA GEORGE

    IPC: G11C7/02 ,  G11C11/24 ,  G11C11/40

    Abstract: D.C. STABLE SEMICONDUCTOR MEMORY CELL Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's . The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

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