公开(公告)号：DE19953383A1

公开(公告)日：2000-06-21

申请号：DE19953383

申请日：1999-11-06

Applicant: IBM

Inventor： CLOUSER PAUL LEE ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN

IPC: G06F3/14 ,  G09G5/36 ,  G09G5/395

Abstract: Two pairs of differential signal lines provided for each graphic port signal are routed close to each other on mother board selected from a group consisting of system chip set and graphic chip. The performance of the graphic port is enhanced, utilizing differential signaling between each of the signal line. - DETAILED DESCRIPTION - INDEPENDENT CLAIMS are also included for the following: - (a) Accelerated graphic port performance enhancing apparatus; - (b) Enhanced accelerated graphic port

公开(公告)号：CA2285878A1

公开(公告)日：2000-05-12

申请号：CA2285878

申请日：1999-10-15

Applicant: IBM

Inventor： NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN ,  CLOUSER PAUL LEE

IPC: G06F3/14 ,  G09G5/36 ,  G09G5/00

Abstract: An accelerated graphic port connection is adapted for differential signaling. Two signal lines are provided for each graphic port and chipset connection signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. An enhanced graphic chip and chipset includes drivers and receivers capable of handling the differential signaling. The resulting accelerated graphic port architecture supports clocking data on both edges as well as source synchronous clocking. The enhanced accelerated graphic port architecture also supports split transactions, deep read pipelining, and the addition of new bus synchronization commands.