MICROCODE CONTROL APPARATUS UTILIZING PROGRAMMABLE LOGIC ARRAY CIRCUITS

    公开(公告)号:CA2006243C

    公开(公告)日:1994-03-15

    申请号:CA2006243

    申请日:1989-12-20

    Applicant: IBM

    Abstract: MICROCODE CONTROL APPARATUS UTILIZING PROGRAMMABLE LOGIC ARRAY CIRCUITS To provide for efficient use of computer microcodes, a firmware structure containing a mainline programmable logic array circuit and at least one subroutine programmable logic array circuit may be used. As the states of the mainline programmable logic array circuit is sequenced, the data bits representing the encode number field in its OR array is compared with the data bits representing the encode number field of the AND array of the subroutine programmable logic array circuit. If a match is made, the mainline programmable logic array circuit suspends its operation and sequencing of the subroutine programmable logic array circuit begins, in order to perform the function required. Upon completion of the function, control is automatically transferred from the subroutine programmable logic array circuit back to the mainline programmable logic array circuit, at the point where it was suspended. By nesting a plurality of subroutine programmable logic array circuits, a plurality of functions, many of which may be performed simultaneously, can take place.

    2.
    发明专利
    未知

    公开(公告)号:DE68926851D1

    公开(公告)日:1996-08-22

    申请号:DE68926851

    申请日:1989-12-13

    Applicant: IBM

    Abstract: A microcode control apparatus utilizing program logic array circuits is described. A firmware structure containing a mainline programmable logic array circuit and at least one subroutine programmable logic array circuit may be used to provide for efficient use of computer microcodes. As the states of the mainline programmable logic array circuit are sequenced, the data bits representing the encode number field in its OR array are compared with the data bits representing the encode number field of the AND array of the subroutine programmable logic array circuit. If a match is made, the mainline programmable logic array circuit suspends its operation and sequencing of the subroutine programmable logic array circuit begins, in order to perform the function required. Upon completion of the function, control is automatically transferred from the subroutine programmable logic array circuit back to the mainline programmable logic array circuit, at the point where it was suspended. By nesting a plurality of subroutine programmable logic array circuits, a plurality of functions, many of which may be performed simultaneously, can take place.

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