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    Data acquisition and control system including dynamic interrupt capability
    1.
    发明授权
    Data acquisition and control system including dynamic interrupt capability 失效
    数据采集​​和控制系统包括动态中断能力

    公开(公告)号：US3905025A

    公开(公告)日：1975-09-09

    申请号：US46133774

    申请日：1974-04-16

    Applicant: IBM

    Inventor： DAVIS MICHAEL I ,  LOFFREDO JOHN M ,  WISE LARRY E ,  RICKARD PATRICK L

    IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F3/00

    CPC classification number: G06F9/4812 ,  G06F9/462 ,  G06F9/4818 ,  G06F13/26

    Abstract: This data acquisition and control system includes many features for enhancing real time response to external or internal conditions. One feature relates to the use of multiple processor control circuits which can be switched between active and inactive status for controlling the performance of processor operations as a function of the level of priority of received interrupt service requests. Another feature pertains to I/O devices attached to the processor. These I/O devices include means for retaining data dynamically allocable by the processor program for specifying assigned interrupt levels and/or for identifying the requisite servicing subroutine in the processor to permit rapid response when an interrupt service is granted. The devices monitor their own status and provide a summary bit to the processor identifying whether or not a status data interchange is required. Multiple masking allows the processor to select between masking all interrupts, interrupts from any source on one or more interrupt priority levels, interrupts from a particular device or devices, or any combination of these.

    Abstract translation: 该数据采集和控制系统包括许多功能，用于增强对外部或内部条件的实时响应。 一个特征涉及使用多个处理器控制电路，其可以在主动和非活动状态之间进行切换，以根据接收的中断服务请求的优先级来控制处理器操作的性能。 另一个特征涉及连接到处理器的I / O设备。 这些I / O设备包括用于保留由处理器程序动态分配的用于指定分配的中断级别的数据和/或用于在处理器中识别必需的服务子例程以允许在给予中断服务时的快速响应的装置。 设备监控自己的状态，并向处理器提供摘要位，识别是否需要状态数据交换。 多重屏蔽允许处理器在一个或多个中断优先级别的屏蔽所有中断，任何源的中断，特定设备或设备的中断或这些的任何组合之间进行选择。

    SINGLE PHYSICAL MAIN STORAGE SHARED BY TWO OR MORE PROCESSORS EXECUTING RESPECTIVE OPERATING SYSTEMS
    2.
    发明专利
    SINGLE PHYSICAL MAIN STORAGE SHARED BY TWO OR MORE PROCESSORS EXECUTING RESPECTIVE OPERATING SYSTEMS 未知

    公开(公告)号：CA2009548C

    公开(公告)日：1996-07-02

    申请号：CA2009548

    申请日：1990-02-07

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUAREZ GUSTAVO A

    IPC: G06F9/46 ,  G06F9/50 ,  G06F11/16 ,  G06F12/02 ,  G06F13/18 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F12/00

    Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/37C peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    3.
    发明专利
    未知

    公开(公告)号：BR9002304A

    公开(公告)日：1991-08-06

    申请号：BR9002304

    申请日：1990-05-17

    Applicant: IBM

    Inventor： DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  BAKER ERNEST D ,  SUAREZ GUSTAVO A

    IPC: G06F9/46 ,  G06F9/50 ,  G06F11/16 ,  G06F12/02 ,  G06F13/18 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/14

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors dirertly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    SERVICING INTERRUPT REQUESTS IN A DATA PROCESSING SYSTEM WITHOUT USING THE SERVICES OF AN OPERATING SYSTEM
    7.
    发明专利
    SERVICING INTERRUPT REQUESTS IN A DATA PROCESSING SYSTEM WITHOUT USING THE SERVICES OF AN OPERATING SYSTEM 未知

    公开(公告)号：CA2009529C

    公开(公告)日：1994-07-12

    申请号：CA2009529

    申请日：1990-02-07

    Applicant: IBM

    Inventor： DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R

    IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F11/00 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/24 ,  G06F13/28 ,  G06F15/173 ,  G06F15/177 ,  G11C29/00 ,  G06F9/00

    Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    MICROCODE CONTROL APPARATUS UTILIZING PROGRAMMABLE LOGIC ARRAY CIRCUITS
    8.
    发明专利
    MICROCODE CONTROL APPARATUS UTILIZING PROGRAMMABLE LOGIC ARRAY CIRCUITS 未知

    公开(公告)号：CA2006243C

    公开(公告)日：1994-03-15

    申请号：CA2006243

    申请日：1989-12-20

    Applicant: IBM

    Inventor： CONCHA FERNANDO ,  LOFFREDO JOHN M

    IPC: G06F9/22 ,  G06F9/26

    Abstract: MICROCODE CONTROL APPARATUS UTILIZING PROGRAMMABLE LOGIC ARRAY CIRCUITS To provide for efficient use of computer microcodes, a firmware structure containing a mainline programmable logic array circuit and at least one subroutine programmable logic array circuit may be used. As the states of the mainline programmable logic array circuit is sequenced, the data bits representing the encode number field in its OR array is compared with the data bits representing the encode number field of the AND array of the subroutine programmable logic array circuit. If a match is made, the mainline programmable logic array circuit suspends its operation and sequencing of the subroutine programmable logic array circuit begins, in order to perform the function required. Upon completion of the function, control is automatically transferred from the subroutine programmable logic array circuit back to the mainline programmable logic array circuit, at the point where it was suspended. By nesting a plurality of subroutine programmable logic array circuits, a plurality of functions, many of which may be performed simultaneously, can take place.

    9.
    发明专利
    未知

    公开(公告)号：BR9002297A

    公开(公告)日：1991-08-06

    申请号：BR9002297

    申请日：1990-05-16

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUZREZ GUSTAVO A

    IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F13/00

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

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