公开(公告)号：SG71076A1

公开(公告)日：2000-03-21

申请号：SG1997006258

申请日：1997-12-05

Applicant: IBM

Inventor： COOK ROBERT K ,  GRUSZECKI CRAIG R ,  PASSARO MARK A ,  SCHOLL FREDERICK A

IPC: H01L21/02 ,  H01L21/82 ,  H01L21/3205

Abstract: The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.

公开(公告)号：CA1227456A

公开(公告)日：1987-09-29

申请号：CA509770

申请日：1986-05-22

Applicant: IBM

Inventor： COOK ROBERT K ,  SHEPARD JOSEPH F

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/70

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

公开(公告)号：MY124334A

公开(公告)日：2006-06-30

申请号：MYPI9705832

申请日：1997-12-04

Applicant: IBM

Inventor： COOK ROBERT K ,  GRUSZECKI CRAIG R ,  PASSARO MARK A ,  SCHOLL FREDERICK A

IPC: H01L21/20 ,  H01L21/02

Abstract: THE PRESENT INVENTION PROVIDES A METHOD FOR FABRICATING A CAPACITOR (42) WITHIN A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF FORMING OPENINGS (18,20) IN AN OXIDE DIELECTRIC (14) TO REACH A LOWER CONDUCTOR LAYER (10) WHICH WILL SERVE AS A LOWER CONDUCTOR PLATE OF THE CAPACITOR; DEPOSITING CAPACITOR ELECTRODE MATERIAL, SUCH AS TUNGSTEN TO FILL THE OPENINGS TO FROM A CAPACITOR ELECTRODE AND PLANARIZING THE FILLED OPENINGS USING CHEMICAL/MECHANICAL POLISH; DEPOSITING A SELECTED OXIDE CAPACITOR DIELECTRIC (30) OVER THE CAPACITOR ELECTRODES AND PATTERING THE CAPACITOR DIELECTRIC WITH PHOTORESIST (32)TO LEAVE DIELECTRIC COVERING THE AREA OF THE CAPACITOR ELECTRODES; STRIPPING AWAY THE PHOTORESIST; ADDING AN UPPER CONDUCTOR LAYER (40) ON TOP OF THE CAPACITOR DIELECTRIC TO SERVE AS THE TOP PLATE OF THE CAPACITOR. THE ABOVE STEPS MAY BE REPEATED TO FROM MULTIPLE LAYERS OF CAPACITORS WITHIN THE SEMICONDUCTOR DEVICE.