公开(公告)号：CA2131668A1

公开(公告)日：1995-06-24

申请号：CA2131668

申请日：1994-09-08

Applicant: IBM

Inventor： GALLI CAROL ,  HSU LOUIS L ,  OGURA SEIKI ,  SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L21/31

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with SiO2 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the SiO2 fill (22) is planarized. Finally, the SiO2 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill-substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.

公开(公告)号：CA1277780C

公开(公告)日：1990-12-11

申请号：CA564542

申请日：1988-04-19

Applicant: IBM

Inventor： MONKOWSKI MICHAEL D ,  SHEPARD JOSEPH F

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/08

Abstract: A novel vertical bi-polar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter and a process of forming such a device. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being continuous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.

公开(公告)号：DE10352068A1

公开(公告)日：2004-05-27

申请号：DE10352068

申请日：2003-11-07

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL ,  SHEPARD JOSEPH F

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H04J1/16 ,  H04J3/14

Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

公开(公告)号：DE10320029A1

公开(公告)日：2003-12-04

申请号：DE10320029

申请日：2003-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOLDBACH MATTHIAS ,  HAUF MANFRED ,  JAMMY RAIARAO ,  MCSTAY IRENE ,  ROUSSEAU JEAN-MARC ,  SCHROEDER UWE ,  SCHUMANN DIRK ,  SEIDL HARALD ,  SELL BERNHARD ,  SHEPARD JOSEPH F ,  TEWS HELMUT

IPC: H01L21/02 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/8242 ,  H01L23/48 ,  H01L27/108

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：BR9304315A

公开(公告)日：1994-05-31

申请号：BR9304315

申请日：1993-10-21

Applicant: IBM

Inventor： BUTI TAQI N ,  HSU LOUIS ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/90 ,  H01L21/283

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：CA1250669A1

公开(公告)日：1989-02-28

申请号：CA549183

申请日：1987-10-13

Applicant: IBM

Inventor： GIAMMARCO NICHOLAS J ,  GIMPELSON ALEXANDER ,  KAPLITA GEORGE A ,  LOPATA ALEXANDER D ,  SCADUTO ANTHONY F ,  SHEPARD JOSEPH F

IPC: H01L21/302 ,  G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/266 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/70

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls. In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.

公开(公告)号：CA2131668C

公开(公告)日：1999-03-02

申请号：CA2131668

申请日：1994-09-08

Applicant: IBM

Inventor： GALLI CAROL ,  HSU LOUIS L ,  OGURA SEIKI ,  SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L21/31

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

公开(公告)号：DE69307274D1

公开(公告)日：1997-02-20

申请号：DE69307274

申请日：1993-10-05

Applicant: IBM

Inventor： BUTI TAQI N ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F ,  HSU LOUIS LU-CHEN

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/535

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：CA1227456A

公开(公告)日：1987-09-29

申请号：CA509770

申请日：1986-05-22

Applicant: IBM

Inventor： COOK ROBERT K ,  SHEPARD JOSEPH F

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/70

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

公开(公告)号：CA1115856A

公开(公告)日：1982-01-05

申请号：CA322415

申请日：1979-02-27

Applicant: IBM

Inventor： GARBARINO PAUL L ,  REVITZ MARTIN ,  SHEPARD JOSEPH F

IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/762 ,  H01L21/225

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a dielectric layer of reflowed phosphosilicate glass (PSG) on top surface of a polycrystalline silicon layer which may be doped by phosphorous impurities diffusing from PSG.