公开(公告)号：US3898444A

公开(公告)日：1975-08-05

申请号：US42944773

申请日：1973-12-28

Applicant: IBM

Inventor： CORDI VINCENT A ,  GURSKI CHESTER S

IPC: G06F11/16 ,  H03K21/40 ,  H03K21/34

CPC classification number: H03K21/40

Abstract: This specification discloses a binary counter with two channels each consisting of a binary counter with ripple carry. Both channels store the same binary number, and to advance the count, a pulse is first applied to the input to one counter and thereafter applied to the input of the other counter. The output of each stage in one counter is Exclusive Ored with the output of the same stage in the other counter. The results of this Exclusive ORing is analyzed with additional logic circuitry to determine if the counts in the two channels are or are not equal. If they are not equal the analysis determines which of the counters contains the higher count, and if the difference in the counts is greater than one. This information is then used to find which of the channels is in error and whether the error is a transient error or an error resulting from a hard failure in one of the channels.

Abstract translation: 本说明书公开了一种具有两个通道的二进制计数器，每个通道由具有波纹携带的二进制计数器组成。 两个通道存储相同的二进制数，并且为了提前计数，首先将脉冲施加到一个计数器的输入，然后施加到另一个计数器的输入。 一个计数器中每个级的输出是独占的，与另一个计数器中相同级的输出相同。 通过额外的逻辑电路分析该异或运算的结果，以确定两个通道中的计数是否相等。 如果它们不相等，则分析确定哪个计数器包含较高的计数，并且计数的差异大于1。 然后，该信息用于查找哪些通道是错误的，以及该错误是否是一个通道中的硬故障引起的瞬态错误或错误。

公开(公告)号：US3893070A

公开(公告)日：1975-07-01

申请号：US43153074

申请日：1974-01-07

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CORDI VINCENT A ,  HSIAO MU-YUE ,  SHIFFRIN BARRY N ,  GLICK ELLIS W

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10

CPC classification number: G06F11/1048

Abstract: An error correction and detection circuit includes a modular encoder that provides the minimum number of check bits for encoding a particular number of data bits. Means is provided for combining several units to produce the minimum number of code bits when a larger data word is to be encoded. A storage hierarchy system using this error correction circuit is also disclosed.

Abstract translation: 纠错和检测电路包括一个模块化编码器，其提供用于编码特定数量的数据位的最小数量的校验位。 提供了用于组合几个单元以在要编码较大数据字时产生最小数量的码位的装置。 还公开了一种使用该纠错电路的存储层级系统。

公开(公告)号：US3889241A

公开(公告)日：1975-06-10

申请号：US32927273

申请日：1973-02-02

Applicant: IBM

Inventor： CORDI VINCENT A ,  GURSKI CHESTER S

IPC: G06F3/06 ,  G06F7/08 ,  G06F7/22 ,  G06K17/00 ,  G06Q40/00 ,  G06F15/40 ,  G11C19/00

CPC classification number: G06K17/00 ,  G06K2017/0038

Abstract: A shift register store and associated controls store randomly entered classes of data records and output the data records on request by specific class in the identical order in which the records of the class were entered into the register. Records are compacted in the register so that no blank character codes exist between records. Blank codes exist only at the end of all valid records on the register. The register and controls and particularly useful in proof/inscribe/sort apparatus of the type used in bank proofing departments to permit the economic use of only one tape advance/print mechanism to produce specific class tapes for a multiplicity of sorter pockets, the documents sorted into each pocket being of the same class. The register and controls are useful in other environments, e.g., to buffer data from a plurality of terminals in a teleprocessing system from key-to-tape (or disk) entry systems, from multi-station inquiry and data collection systems, and in message concentrator application.

Abstract translation: 移位寄存器存储器和相关控件存储随机输入的数据记录类别，并按照特定类别的请求输出数据记录，其类型记录被输入到寄存器中。 记录在记录中被压缩，因此记录之间不存在任何空白的字符代码。 空白代码只存在于注册表上所有有效记录的末尾。 注册和控制，特别适用于银行打样部门使用的类型的证明/铭文/分类设备，以允许经济使用一个磁带预先/打印机制，为多个分拣机口袋生成特定的类磁带，文件分类 进入每个口袋是同一个类。 寄存器和控制在其他环境中是有用的，例如，从远程处理系统中的多个终端从密钥到磁带（或磁盘）入口系统，来自多站查询和数据收集系统以及消息中的数据缓冲数据 集中应用。

公开(公告)号：DE2655829A1

公开(公告)日：1977-07-07

申请号：DE2655829

申请日：1976-12-09

Applicant: IBM

Inventor： CAPOZZI ANTHONY J ,  CORDI VINCENT A ,  EDSON BRUCE A

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0866 ,  G11C9/06

公开(公告)号：CA1033847A

公开(公告)日：1978-06-27

申请号：CA228419

申请日：1975-05-30

Applicant: IBM

Inventor： CORDI VINCENT A ,  EDSON BRUCE A

IPC: G06F13/00 ,  G06F11/14 ,  G06F12/08 ,  G06F12/16

Abstract: This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.

公开(公告)号：FR2325151A1

公开(公告)日：1977-04-15

申请号：FR7404778

申请日：1974-01-29

Applicant: IBM

Inventor： CORDI VINCENT A ,  GURSKI CHESTER S

IPC: G06K17/00 ,  G11C19/00 ,  G06F3/04

公开(公告)号：CA993554A

公开(公告)日：1976-07-20

申请号：CA167871

申请日：1973-03-30

Applicant: IBM

Inventor： CORDI VINCENT A ,  NICKEL TED Y

IPC: G06F12/08 ,  G06F12/12 ,  G11C19/08

Abstract: A Least Recently Used (LRU) Algorithm is implemented in a dynamically ordered, magnetic bubble domain shift register to enhance both the speed and cost reduction of paging between levels of a storage hierarchy containing a large quantity of data.

公开(公告)号：FR2277407A1

公开(公告)日：1976-01-30

申请号：FR7516576

申请日：1975-05-23

Applicant: IBM

Inventor： CORDI VINCENT A ,  EDSON BRUCE A

IPC: G06F13/00 ,  G06F11/14 ,  G06F12/08 ,  G06F12/16 ,  G11C9/06

Abstract: This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.