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公开(公告)号：DE1962411A1
公开(公告)日：1970-07-02
申请号：DE1962411
申请日：1969-12-12
Applicant: IBM
Inventor： COURT GREESON JUN JAMES , ELMORE NEWCOMB CHARLES
Abstract: 1285085 Matrix displays INTERNATIONAL BUSINESS MACHINES CORP 28 Nov 1969 [19 Dec 1968] 58279/69 Index G4H 3G 6A 6B 6E 7A1 7B 86 9E 13D Display apparatus comprises a gas panel (1, 2) Fig.3 (not shown), first and second crossed conductor arrays X1-X21, (T1-T21) and associated with each array a plurality of selection lines 30- 36, (230-236) each capacitively coupled to a different plurality of the associated conductors, the arrangement being such that the same number and at least two lines are energized to apply firing potential to a conductor. Sustaining potentials of 10 V., 60 c.p.s. are connected, in opposite phase to all X and Y conductors from sources 23, (22) and firing potentials of 600 V., 50 kc/s. are connected in opposite phase to selected conductors from sources 20, (21). The source 20 is connected to the X conductors via amplifiers 40...46 selection lines 30...36 and condensers 50...91. The amplifiers are controlled by a selection register 115 of flip-flops 120...126 supplied with control signals on lines 130...136 and a reset signal on line 137. Applying signals to any selected pair of lines, e.g. 130, 131 sets flipflops 120, 121 to condition amplifiers 40, 41 to pass signals from the source 20 to lines 30, 31 and apply a potential V 1 via each capacitor 50, 52 ...51, 62...&c. to conductors X1...X11. This results in a combined potential of 2V 1 only on conductor X1 and thus with a similar potential on a Y conductor is sufficient to ignite the cell at the intersection of the conductors. The potential on the Y conductor is produced by a similar arrangement. After igniting the registers are cleared and signals applied to further pairs of flip-flops until a picture is built up. The picture is removed by disconnecting the potential from source 23. The maintaining and igniting potentials applied to X and Y conductors need not be equal.
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Patent Agency Ranking
公开(公告)号：DE1804366A1
公开(公告)日：1969-06-19
申请号：DE1804366
申请日：1968-10-22
Applicant: IBM
Inventor： WALKER ARNOLD ROBERT , COURT GREESON JUN JAMES
Abstract: 1,257,316. Absolute value generating circuits. INTERNATIONAL BUSINESS MACHINES CORP. 4 Nov., 1968 [9 Nov., 1967], No. 52180/68. Heading H3W. [Also in Division G4 An absolute value circuit for producing an output signal of one polarity irrespective of the polarity of the input signal comprises a first negative feedback amplifier 1 having two output terminals providing selection devices through respective polarity signals of respective polarities and a further negative feedback amplifier 2 which inverts one signal only. As shown, the respective polarities are selected by diodes in the feedback path of the first amplifier and the signals are fed to the inverting and non- inverting inputs of the second amplifier. Potentiometers adjust the offset to zero and the gain to unity.
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公开(公告)号：DE1524405A1
公开(公告)日：1970-11-26
申请号：DE1524405
申请日：1966-06-04
Applicant: IBM
Inventor： DECLARIS NICHOLAS , COURT GREESON JUN JAMES , BERNARD HORGAN THOMAS
Abstract: 1,121,954. Character recognition. INTERNATIONAL BUSINESS MACHINES CORP. 26 May, 1966 [7 June, 1965], No. 23619/66. Heading G4R. [Also in Division G1] In waveform analyzing apparatus, e.g. for character recognition, predetermined fractions of the total energy content of the waveform are compared with its energy content in various frequency bands. Voltage dividers are used for obtaining the fractions of the total energy. The comparator outputs control logic circuitry to identify the character represented by the waveform, the logic circuitry being enabled through a delay by a peak detector also receiving the waveform. Squarers and integrators are used for measuring energy content.
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公开(公告)号：DE1524297A1
公开(公告)日：1970-07-02
申请号：DE1524297
申请日：1966-12-03
Applicant: IBM
Inventor： COURT GREESON JUN JAMES , JOSEPH KENNEDY JAMES
Abstract: 1,163,608. Drift correction for operational amplifiers. INTERNATIONAL BUSINESS MACHINES CORP. 21 Dec., 1966 [27 Dec., 1965], No. 57204/66. Heading G4G. [Also in Division H3] In a drift compensating circuit, particularly for an operational amplifier, the output of the amplifier 4 is compared at 10 with a reference voltage 11, the output of the comparator 10 being gated at 13 by reset signals 14 and arranged to charge a capacitor 15 which is connected via a buffer amplifier 16 to the input of amplifier 4 so as to compensate for errors due to drift and the initial values of input signals in any of amplifiers 1 . . . 4 at the beginning of a computing cycle. The comparator 10 (Fig. 2) may be formed by an emitter-coupled pair of transistors 20, 22, the output of which is passed by an amplifying transistor 30 to a field-effect transistor AND gate 40 the conductivity of which is controlled by signals at 14 amplified at 41. The system is reset by applying a negativegoing signal at 14 which turns on transistor 41, turning on the AND gate 40, diode 42 isolating the control gate 39. Capacitor 15 follows the output of the comparator 10, providing a compensating signal which is fed back via fieldeffect transistor 50 and resistor 17 (Fig. 1) to the input of the amplifier 4 so as to maintain the output Vo at its zero level. A computing cycle is initiated by feeding a positive-going signal to 14 which cuts off transistors 41, 40, so that the charge remaining on capacitor 15 provides compensation. Figs. 4, 5 (not shown), depict the invention applied to summing and differential amplifiers.
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