公开(公告)号：DE1524444A1

公开(公告)日：1970-08-20

申请号：DE1524444

申请日：1966-12-24

Applicant: IBM

Inventor： WARNER HARDIN WILLIAL ,  JOSEPH KENNEDY JAMES

IPC: G06K11/04 ,  G06K9/16

Abstract: 1,165,720. Pattern recognition. INTERNATIONAL BUSINESS MACHINES CORP. 21 Dec., 1966 [5 Jan., 1966], No. 57198/66. Heading G4R. Apparatus for determining the direction of movement of a body comprises movement circuitry producing signals for moving the body in a first circular path, control circuitry for producing signals for moving the body in a second circular path of different radius under the control of a variable control factor, and indicating circuitry coupled to the movement circuitry producing continuously a signal representative of the direction of movement of the body when moving in the second circular path. In a first embodiment, a flying-spot scanner follows the outline of a character by being fed with sin and cos deflection voltages derived from an oscillator to produce a circle scan whose radius is reduced when the spot is on the character as distinct from the background. The sin and cos voltages and a minus cos voltage also derived from the oscillator are compared with each other and earth to produce signals specifying in which if any of four overlapping 180 degree sectors the direction of movement of the spot lies. Whenever the spot is on the character itself, these signals are enabled to set triggers the outputs of which are decoded in AND gates to specify one of eight compass directions. In a second embodiment, the radius of the scan is increased from 255 degrees after the spot moves on to the character until 30 degrees later. Sin and cos deflection voltages are derived by filters and integrators from selectively-attenuated square waves produced by two triggers controlled by a 12-stage ring counter. Whenever the radius of the scan is increased by deactivating the attenuators, the state of the counter is stored to indicate the direction of movement of the spot. The direction of movement of the spot, thus repetitively determined, specifies the shape of the character for character recognition purposes and enables trapping of the spot within a hollow space in the character to be detected.

公开(公告)号：DE1524297A1

公开(公告)日：1970-07-02

申请号：DE1524297

申请日：1966-12-03

Applicant: IBM

Inventor： COURT GREESON JUN JAMES ,  JOSEPH KENNEDY JAMES

IPC: H03F3/34 ,  G06G7/06 ,  G06G7/122 ,  H03F1/30 ,  G06G7/12

Abstract: 1,163,608. Drift correction for operational amplifiers. INTERNATIONAL BUSINESS MACHINES CORP. 21 Dec., 1966 [27 Dec., 1965], No. 57204/66. Heading G4G. [Also in Division H3] In a drift compensating circuit, particularly for an operational amplifier, the output of the amplifier 4 is compared at 10 with a reference voltage 11, the output of the comparator 10 being gated at 13 by reset signals 14 and arranged to charge a capacitor 15 which is connected via a buffer amplifier 16 to the input of amplifier 4 so as to compensate for errors due to drift and the initial values of input signals in any of amplifiers 1 . . . 4 at the beginning of a computing cycle. The comparator 10 (Fig. 2) may be formed by an emitter-coupled pair of transistors 20, 22, the output of which is passed by an amplifying transistor 30 to a field-effect transistor AND gate 40 the conductivity of which is controlled by signals at 14 amplified at 41. The system is reset by applying a negativegoing signal at 14 which turns on transistor 41, turning on the AND gate 40, diode 42 isolating the control gate 39. Capacitor 15 follows the output of the comparator 10, providing a compensating signal which is fed back via fieldeffect transistor 50 and resistor 17 (Fig. 1) to the input of the amplifier 4 so as to maintain the output Vo at its zero level. A computing cycle is initiated by feeding a positive-going signal to 14 which cuts off transistors 41, 40, so that the charge remaining on capacitor 15 provides compensation. Figs. 4, 5 (not shown), depict the invention applied to summing and differential amplifiers.

公开(公告)号：DE1549756A1

公开(公告)日：1971-04-15

申请号：DE1549756

申请日：1967-03-04

Applicant: IBM

Inventor： WARNER HARDIN WILLIAM ,  JOSEPH KENNEDY JAMES ,  RUSSELL PLUMMER NORMAN

IPC: G06V30/144 ,  G06K9/16

Abstract: 1,117,854. Pattern recognition. INTERNATIONAL BUSINESS MACHINES CORPORATION. 13 Feb., 1967 [14 March, 1966], No. 6710/67. Heading G4R. Apparatus for controlling the movement of a beam of radiation scanning around a pattern comprises means for defining a band of predetermined width extending across the pattern and for defining an area displaced from the band and on the periphery of the pattern, and means for determining when the beam has scanned across the band and area to indicate completion of a scan cycle. The photomultiplier 9 of a flying-spot scanner 5, 9 controls, via AND 47, attenuation 26, 27 of sine and cosine voltages being fed to Y and X integrators 29, 28 providing the vertical and horizontal deflection voltages for the scanner so that the outline of the character to be recognized is followed round. The maximum and minimum vertical deflection voltages during following round are stored at 33, 35 and in order to move to the next character the average of these voltages is compared 31 with the current vertical deflection voltage to control attenuation 26, 27 via AND 39 so that the beam follows an imaginary horizontal boundary to the next character. A voltage divider R11 to R14 specifies the upper and lower limits of a horizontal stop band (which should contain the scan path between characters) to comparators 67, 69 which also receive the vertical deflection voltage to indicate whether the beam is within the stop band at any given time. When the beam has been following round a character for a predetermined time, as indicated by an output at V derived from the photomultiplier 9 being present for this time, and the beam is not in the stop band, a latch 71 is set, thus causing the current vertical and horizontal deflection voltages to be stored at 63, 51, voltage dividers R7 to B10, R3 to R6 supplying predetermined fractions of the stored voltages to comparators 59, 61, 55, 57 to specify the limits of a stop box. The comparators compare these limits with the vertical and horizontal deflection voltages to specify whether the beam is within the stop box at any given time. Setting of the latch 71 enables a latch 81 to be set as soon as the beam is next in the stop band but not in the stop box, and this enables a latch 95 to be set as soon as the beam is next outside both stop band and stop box. Setting of latch 95 allows a latch 99 to be set as soon as the beam is next inside the stop box and this allows a latch 103 to be set as soon as the beam next leaves the stop box. Setting of latch 103 applies signal CCDO to the recognition system 13 to indicate completion of following round the character (e.g. to initiate a character recognition scan, the first scan being for normalization).

公开(公告)号：DE1487321A1

公开(公告)日：1969-10-16

申请号：DE1487321

申请日：1966-01-25

Applicant: IBM

Inventor： JOSEPH KENNEDY JAMES

IPC: H03F3/45 ,  H03G1/00 ,  H03F3/68

Abstract: 1,065,208. Transistor amplifying circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 26, 1966 [Feb. 5, 1965], No. 3477/66. Heading H3T. A stage in a variable gain differential direct current amplifier comprises two matched transistors supplied from a current source via two resistance circuits, the values of which are inversely proportional to the currents flowing through them at a predetermined gain level. According to the invention, means are provided responsive to variations in the gain level and controlling the current source so the ratio of the currents flowing in the resistance circuits remains substantially independent of the gain level. The input stage of a D.C. amplifier comprises transistors 11, 12 having as collector load circuits resistors 61, 62 respectively and adjustable potentiometer 60, and being fed via an auxiliary transistor 57. Input signal is applied to the base of transistor 11 via resistor 22 or 23, the base of transistor 12 being earthed and a common emitter impedance being provided in the form of further auxiliary transistor 13, to the base of which gain controlling potentials are applied. The input stage 11, 12 drives, via resistance/capacitance networks 36, 38 and 37, 39 respectively, the bases of a second stage 70, 71 the collectors of which are coupled in a similar manner to an output stage comprising transistors 75, 90. Negative feedback is applied from the collectors of output transistors 75, 90 to the bases of transistors 70, 71 via resistors 76, 99 respectively. Any unbalanced component in the drive to transistors 70, 71 is detected by means of a potentiometer 33, 34 and applied to the base of transistor 45, whereas the corresponding unbalanced component at the collectors of transistors 11, 12 is detected by means of potentiometer 31, 32 and applied to the base of transistor 46. Transistors 45, 46 have a common emitter circuit resistor 49 and are coupled respectively to transistors 52, 53 which have common emitter circuit resistor 54. Transistor 53 has collector load resistor 56 and is direct coupled to the base of auxiliary transistor 57, to provide degenerative feedback for any unbalanced component.