公开(公告)号：DE3069749D1

公开(公告)日：1985-01-17

申请号：DE3069749

申请日：1980-07-10

Applicant: IBM

Inventor： DAS GUPTA SUMIT ,  GOEL PRABHAKAR ,  WILLIAMS THOMAS WALTER

IPC: G06F7/00 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26

Abstract: According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in/scan-out operations on test data (test patterns, result patterns), but not both, If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art. If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.