公开(公告)号：DE2728318A1

公开(公告)日：1978-01-05

申请号：DE2728318

申请日：1977-06-23

Applicant: IBM

Inventor： EICHELBERGER EDWARD BAXTER ,  MUEHLDORF EUGEN IGOR ,  WALTHER RONALD GENE ,  WILLIAMS THOMAS WALTER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20

Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

公开(公告)号：DE2720863A1

公开(公告)日：1978-01-05

申请号：DE2720863

申请日：1977-05-10

Applicant: IBM

Inventor： EICHELBERGER EDWARD BAXTER ,  WILLIAMS THOMAS WALTER

IPC: G06F7/00 ,  G01R31/3185 ,  G06F11/22 ,  G11C19/00 ,  G06F13/06

Abstract: The disclosure relates to LSSD systems for use in digital computers and the like. More particularly, to an organization of logic in such systems to render the clock networks testable with minimal overhead. The advantages of the practice of the invention are particularly apparent and enhanced when the invention is employed in a Level Sensitive Scan Design (LSSD) System generally of the type disclosed in U.S. Pat. No. 3,783,254 and U.S. patent application Ser. No. 701,052, filed June 30, 1976.

公开(公告)号：DE2728676A1

公开(公告)日：1978-01-12

申请号：DE2728676

申请日：1977-06-25

Applicant: IBM

Inventor： EICHELBERGER EDWARD BAXTER ,  MUEHLDORF EUGEN IGOR ,  WALTHER RONALD GENE ,  WILLIAMS THOMAS WALTER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G11C7/00 ,  H01L27/04

Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

公开(公告)号：IT1150035B

公开(公告)日：1986-12-10

申请号：IT2369180

申请日：1980-07-25

Applicant: IBM

Inventor： SUMIT DAS GUPTA ,  PRABHAKAR GOEL ,  WILLIAMS THOMAS WALTER

IPC: G06F7/00 ,  G01R31/3185 ,  G06F11/22 ,  G06F

Abstract: According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in/scan-out operations on test data (test patterns, result patterns), but not both, If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art. If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.

公开(公告)号：DE3069749D1

公开(公告)日：1985-01-17

申请号：DE3069749

申请日：1980-07-10

Applicant: IBM

Inventor： DAS GUPTA SUMIT ,  GOEL PRABHAKAR ,  WILLIAMS THOMAS WALTER

IPC: G06F7/00 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26

Abstract: According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in/scan-out operations on test data (test patterns, result patterns), but not both, If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art. If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.

公开(公告)号：DE2962713D1

公开(公告)日：1982-06-24

申请号：DE2962713

申请日：1979-09-12

Applicant: IBM

Inventor： BROWN DAVID JOHN ,  WALTHER RONALD G ,  WILLIAMS THOMAS WALTER ,  WRIGGLESWORTH MICHAEL DENIS

IPC: G01R31/3185 ,  G06F7/00 ,  G06F11/22 ,  G11C19/00 ,  G11C19/14 ,  G11C19/28 ,  H03K3/027 ,  H03K3/037 ,  H03K3/286 ,  H03K5/15 ,  H03K19/20 ,  H03K23/00 ,  H03K19/003 ,  G11C29/00

Abstract: A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a 'D' type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.

公开(公告)号：DE2729053A1

公开(公告)日：1978-01-12

申请号：DE2729053

申请日：1977-06-28

Applicant: IBM

Inventor： EICHELBERGER EDWARD BAXTER ,  MUEHLDORF EUGEN IGOR ,  WALTHER RONALD GENE ,  WILLIAMS THOMAS WALTER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  B07C5/344 ,  G06F11/00

Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.