公开(公告)号：JP2001249805A

公开(公告)日：2001-09-14

申请号：JP2001032619

申请日：2001-02-08

Applicant: IBM

Inventor： KEVIN ARTHUR CHALOT ,  KONIGSBURG BRIAN R ,  DAVE STEVEN LEVITAN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/34

Abstract: PROBLEM TO BE SOLVED: To generate an instruction takeout address within timing restriction of a gigahertz processor system by executing a microprocessor instruction. SOLUTION: All address generating unit suitable for generating a set of branching target addresses corresponding to a set of received instructions and a multiplexer constituted to receive the set of branching target addresses as input are included in an instruction processing unit(IPU) 211. Output of the multiplexer is supplied to an instruction address takeout register. An address incremeter suitable for generating the next instruction address corresponding to the next sequential instruction address following the instruction address corresponding to the received set of addresses is included in the IPU 211.