公开(公告)号：JPH10283179A

公开(公告)日：1998-10-23

申请号：JP7380398

申请日：1998-03-23

Applicant: IBM

Inventor： JORDAN PAUL J ,  KONIGSBURG BRIAN R ,  LE HUNG QUI ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a pipeline type data processor for performing the random execution and inference execution of instructions by allocating intrinsic identifiers to the respective instructions and using the identifiers again during the execution of a program inside a data processing system. SOLUTION: This data processing system is provided with an input circuit and a memory for storing plural control values corresponding to the identifiers of plural targets and the memory is provided with first and second banks. Also, a target identification circuit for generating plural target identification values and continuously allocating the respective target identifiers to the corresponding instructions is provided as well. When the target identification values corresponding to the plural control values are allocated inside the first and second banks, the target identification circuit selectively reallocates the first part of the plural target identification values corresponding to the first part of the plural control values inside the first bank. The data processing system 100 is provided with a pipeline type CPU 110 and the CPU 110 is connected to other various constituting elements by a system bus 112.

公开(公告)号：JP2001249805A

公开(公告)日：2001-09-14

申请号：JP2001032619

申请日：2001-02-08

Applicant: IBM

Inventor： KEVIN ARTHUR CHALOT ,  KONIGSBURG BRIAN R ,  DAVE STEVEN LEVITAN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/34

Abstract: PROBLEM TO BE SOLVED: To generate an instruction takeout address within timing restriction of a gigahertz processor system by executing a microprocessor instruction. SOLUTION: All address generating unit suitable for generating a set of branching target addresses corresponding to a set of received instructions and a multiplexer constituted to receive the set of branching target addresses as input are included in an instruction processing unit(IPU) 211. Output of the multiplexer is supplied to an instruction address takeout register. An address incremeter suitable for generating the next instruction address corresponding to the next sequential instruction address following the instruction address corresponding to the received set of addresses is included in the IPU 211.

公开(公告)号：JP2006114036A

公开(公告)日：2006-04-27

申请号：JP2005294193

申请日：2005-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CURRAN BRIAN WILLIAM ,  KONIGSBURG BRIAN R ,  HUNG QUI LE ,  ARNOLD LUICK DAVID ,  NGUYEN DUNG QUOC

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3885

Abstract: PROBLEM TO BE SOLVED: To simultaneously execute a plurality of instructions, and thereby efficiently use hardware resources to increase the whole processor throughput.
SOLUTION: A resource vector representing a necessary resource is encoded to a resource field, and the resource field is decoded in the subsequent step in order to derive the resource vector. The resource field is stored in an instruction cache related to respective program instructions. A processor operates in a simultaneous multithreading mode. When validity of a resource is equal to or exceeds a resource requirement of an instruction group, instructions thereof are simultaneously dispatched to hardware resources. A starting bit is inserted into one of the program instructions in order to define the instruction group. The hardware resource is, in particular, an execution unit such as a fixed decimal point unit 56, a load/store unit 58, a floating decimal point unit 60 or a branch processing unit 61.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：同时执行多个指令，从而有效地使用硬件资源来增加整个处理器的吞吐量。 解决方案：将表示必要资源的资源向量编码到资源字段，并且在后续步骤中对资源字段进行解码，以便导出资源向量。 资源字段存储在与各个程序指令相关的指令高速缓存中。 处理器以同时多线程模式运行。 当资源的有效性等于或超过指令组的资源需求时，其指令被同时发送到硬件资源。 为了定义指令组，将起始位插入其中一个程序指令。 硬件资源特别是诸如固定小数点单元56，加载/存储单元58，浮动小数点单元60或分支处理单元61之类的执行单元。（C）2006， JPO＆NCIPI

公开(公告)号：CA2332141A1

公开(公告)日：2001-08-17

申请号：CA2332141

申请日：2001-01-23

Applicant: IBM

Inventor： KONIGSBURG BRIAN R ,  CHIAROT KEVIN ARTHUR ,  LEVITAN DAVE STEPHEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/34

Abstract: A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instruction s from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in th e set of instructions for which branch instruction information must be recorded exceeds the capacity o f IPU to record the branch instruction information in a single cycle. The IPU may include an address generation unit suitable for generating a set of branch target addresses corresponding to th e set of received instructions and a multiplexer configured to receive as inputs the set of branch target addresses. The output of the multiplexer is provided to the instruction address fetch register. The IPU may include an address incrementer suitable for generating a next instruction address corresponding to the next sequential instruction address following the instruction address correspondi ng to the received set of addresses. In this embodiment, the next instruction address comprises an inp ut to the multiplexer. The IPU may further include selector logic adapted to select the next instruction address as the output of the multiplexer if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to reco rd the branch instruction information in a single cycle. The selector logic is adapted to select as th e output of the multiplexer the branch target address of the first instruction predicted to be taken if the number of branch instructions in the set of instructions for which branch instruction information must be recorded does not exceed the capacity of IPU to record the branch instruction information in a single cycle.