公开(公告)号：JP2002100985A

公开(公告)日：2002-04-05

申请号：JP2001221160

申请日：2001-07-23

Applicant: IBM

Inventor： DAVID WILLIAM BOOSURAA ,  MARK EDWARD DEAN ,  NGO HUNG CAI ,  ANDREW CHRISTIAN ZIMMERMAN

IPC: H03L7/22 ,  H03L7/08 ,  H03L7/23 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for adjusting the generated frequency, especially a frequency synthesizer capable of performing the frequency adjustment of high resolution at high speed, using a multi-stage frequency synthesizer. SOLUTION: The initial stage of the frequency synthesizer is a conventional phase-locked loop connected to a dynamically variable frequency divider. There are one or more intermediate stages provided with the forward part of the phase-locked loop connected to the dynamically variable frequency divider for performing feedback through a fixed frequency divider. The final stage is provided with the forward part of the phase-locked loop connected to a different fixed frequency divider for performing feedback through the fixed frequency divider. By changing the frequency division constant of the variable frequency divider of a circuit, fine frequency adjustment is performed at a very high speed. The accuracy of the adjustment depends on the relative value of the frequency divider and the number of the intermediate stages inside a system.

公开(公告)号：JP2002171247A

公开(公告)日：2002-06-14

申请号：JP2001221146

申请日：2001-07-23

Applicant: IBM

Inventor： DAVID WILLIAM BOOSURAA ,  MARK EDWARD DEAN ,  NGO HUNG CAI ,  ANDREW CHRISTIAN ZIMMERMAN

IPC: H03L7/22 ,  G06F13/00 ,  G06F15/163 ,  G06F15/177 ,  H03L7/23 ,  H04L7/00

Abstract: PROBLEM TO BE SOLVED: To provide a node synchronization method and apparatus which can be used for a different machine kind mixing computer system in which a common system clock is not shared. SOLUTION: Time stamps are added to a transaction request. These time stamps can be registers to be incremented by a system clock based on a time value. Nodes are respectively provided with exclusive system clocks, and the frequencies of those clocks can be deviated. When the deviation of the value is large, data updated by a multi-processor computer system can be lost. The relative phase of a master time register to one or more slave time registers is monitored. A frequency synthesizer whose resolution is high and whose high speed frequencies are adjustable is connected to the system clock. When anY phase shift is detected in the master and slave time values, the output of the frequency synthesizer is changed so that the phases of the two signals can be matched into an original state.