公开(公告)号：PH31230A

公开(公告)日：1998-06-16

申请号：PH38364

申请日：1989-03-21

Applicant: IBM

Inventor： CULICAN EDWARD F SR ,  DAVIS JOHN D ,  EWEN JOHN F ,  MCCABE SCOTT A ,  MOSLEY JOSEPH M ,  MULLGRAY ALLAN L JR ,  NOTO PHILIP F ,  PETERSON CLARENCE I JR ,  PRITZLAFF PHILIP E JR

IPC: H01L21/82 ,  H01L27/04 ,  H01L21/822 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/08 ,  H03L331/01

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：CA1312929C

公开(公告)日：1993-01-19

申请号：CA588443

申请日：1989-01-17

Applicant: IBM

Inventor： CULICAN EDWARD F SR ,  DAVIS JOHN D ,  EWEN JOHN F ,  MC CABE SCOTT A ,  MOSLEY JOSEPH M ,  MULLGRAV ALLAN L JR ,  NOTO PHILIP F ,  PETERSON CLARENCE I JR ,  PRITZLAFF PHILIP E JR

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: Analog Macro Embedded In A Digital Gate Array A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal. FI9-88-004

公开(公告)号：CA1277375C

公开(公告)日：1990-12-04

申请号：CA570933

申请日：1988-06-30

Applicant: IBM

Inventor： DAVIS JOHN D ,  MULLGRAV ALLAN L JR

IPC: H03B5/36 ,  H03K3/0231 ,  H03K3/013

Abstract: OSCILLATOR CIRCUIT An oscillator with noise rejection and a fifty percent duty cycle for the on-chip generation and conversion of a sine wave to a square wave, using an external reference crystal. The circuit comprises a low gain current switch including a first and second switching transistors, with the control lines of the switching transistors connected to a reference voltage line. The reference crystal is connected across the control input and the current receiving terminals of the first transistor so that a square wave is obtained at the current receiving terminal of the second transistor. A threshold circuit is included for adjusting the voltage of the square wave signal from the second transistor and applying the adjusted signal to a diode-coupled receiver circuit, which provides the output for the circuit. This oscillator circuit provides a double action noise immunity through the use of a low gain current switch to prevent noise amplification, in combination with a diode-coupled receiver which is affected by noise only during signal transitions. A duty cycle very close to fifty percent is realized by the circuit.