公开(公告)号：CA1263716A

公开(公告)日：1989-12-05

申请号：CA507289

申请日：1986-04-22

Applicant: IBM

Inventor： CULICAN EDWARD F ,  PRITZLAFF PHILIP E JR ,  SCHETTLER HELMUT ,  VAN GOOR KENNETH A

IPC: H03K19/0175 ,  H03K17/60 ,  H03K19/013 ,  H03K19/018 ,  H03K19/088 ,  H03K19/082 ,  H03K19/092

Abstract: A circuit for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. The circuit has particular utility when employed with logic circuits such as "TTL" (Transistor- Transistor Logic) and "DTL" (Diode-Transistor Logic).

公开(公告)号：CA1229428A

公开(公告)日：1987-11-17

申请号：CA490346

申请日：1985-09-10

Applicant: IBM

Inventor： CULICAN EDWARD F ,  PRITZLAFF PHILIP E JR

IPC: H03K19/013 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03K19/088 ,  H03K19/173 ,  H01L27/02

Abstract: The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.

公开(公告)号：PH31230A

公开(公告)日：1998-06-16

申请号：PH38364

申请日：1989-03-21

Applicant: IBM

Inventor： CULICAN EDWARD F SR ,  DAVIS JOHN D ,  EWEN JOHN F ,  MCCABE SCOTT A ,  MOSLEY JOSEPH M ,  MULLGRAY ALLAN L JR ,  NOTO PHILIP F ,  PETERSON CLARENCE I JR ,  PRITZLAFF PHILIP E JR

IPC: H01L21/82 ,  H01L27/04 ,  H01L21/822 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/08 ,  H03L331/01

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：CA1312929C

公开(公告)日：1993-01-19

申请号：CA588443

申请日：1989-01-17

Applicant: IBM

Inventor： CULICAN EDWARD F SR ,  DAVIS JOHN D ,  EWEN JOHN F ,  MC CABE SCOTT A ,  MOSLEY JOSEPH M ,  MULLGRAV ALLAN L JR ,  NOTO PHILIP F ,  PETERSON CLARENCE I JR ,  PRITZLAFF PHILIP E JR

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: Analog Macro Embedded In A Digital Gate Array A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal. FI9-88-004