公开(公告)号：JPH0661505A

公开(公告)日：1994-03-04

申请号：JP13064293

申请日：1993-06-01

Applicant: IBM

Inventor： KEBUIN KOKU CHIYAN ,  SAN HOO DON ,  DEIITAA POORU OIGEN KERUN ,  YANGU HOON RII

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To obtain a flash EEPROM which is operable at a low voltage and has a high resistance to the disturbance and a structure capable of scaling easily. CONSTITUTION: A flash EEPROM having MOS cells is manufactured. At each cell, programming and erase are made by the tunnel effect directed from a write gate 22 to a floating gate 22 and tunnel effect directed from the floating gate 14 to an erase gate 10. Directional dielectrics 16, 24 used are multilayer structure(MLS) oxides composed of thin oxide layers and thin polysilicon layers alternately laminated to form asymmetric layer structures; the uppermost or lowermost layer is thicker than others. In the result of this structure, the oxide shows a directionality i.e., the tunnel effect is easier in one direction than in the reverse direction. The oxides greatly enhance the tunnel effect (recognizable at a low voltage of 4.7 V).