公开(公告)号：JPH04287519A

公开(公告)日：1992-10-13

申请号：JP32832491

申请日：1991-11-18

Applicant: IBM

Inventor： CHINNTE KENTO CHIYAN ,  DENII DANNRII TAN

IPC: H03K19/013 ,  H03K19/086

Abstract: PURPOSE: To provide a high-speed low-power emitter combination logic(ECL) circuit and a non-threshold logic(NTL) circuit using an AC combination complementary push-pull output stage. CONSTITUTION: This circuit 19 combines an AC pulse obtained from the replica of an input signal with the bases of complementary PNP-NPN push-pull transistors 25 and 26 using two capacitors 34 and 35 to generate a large transient current, so that high-speed operation with extremely less DC power consumption is realized. By this combination structure, a proper logic level is kept using an extremely less switching current in a logic (current switching) stage, and also influence to switching speed due to large pull-up resistors 27 and 28 in the logic stage is prevented.