公开(公告)号：FR2276691A1

公开(公告)日：1976-01-23

申请号：FR7516564

申请日：1975-05-23

Applicant: IBM

Inventor： DENNARD ROBERT M ,  RIDEOUT VINCENT L ,  WALKER EDWARD J

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L27/088 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L21/74 ,  H01L29/76 ,  G11C11/34

Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.