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公开(公告)号:GB2581755B
公开(公告)日:2020-12-23
申请号:GB202008806
申请日:2018-11-22
Applicant: IBM
Inventor: SHAWN PETER FETTEROLF , MICHAEL A GUILLORN , DANIEL CORLISS , DERREN NEYLON DUNN
Abstract: An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.
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公开(公告)号:GB2581755A
公开(公告)日:2020-08-26
申请号:GB202008806
申请日:2018-11-22
Applicant: IBM
Inventor: SHAWN PETER FETTEROLF , MICHAEL A GUILLORN , DANIEL CORLISS , DERREN NEYLON DUNN
Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include an electrical design necessary for the operation of the semiconductor circuit, and white space, which has no electrical design. The method may include inserting an optical design into the white space of the photomask design for the semiconductor circuit. The optical design may have known optical patterns for validating the semiconductor circuit design. In an embodiment of the invention, the optical design may be physically isolated from the electrical design. In another embodiment of the invention, the optical design may comprise one or more photomask layers and overlay the electrical design. In another embodiment of the invention, the optical design may comprise covershapes.
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