公开(公告)号：CA936598A

公开(公告)日：1973-11-06

申请号：CA122497

申请日：1971-09-10

Applicant: IBM

Inventor： DEWITT D

IPC: H03K17/14 ,  H03K17/60 ,  H03K19/086

公开(公告)号：SE329213B

公开(公告)日：1970-10-05

申请号：SE791264

申请日：1964-06-29

Applicant: IBM

Inventor： BUTLER J ,  DEWITT D

IPC: H01L21/00 ,  H01L21/3063 ,  H01L29/00 ,  H01L7/56

Abstract: 1,060,755. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 27; 1964 [June 28, 1963], No. 21924/64. Heading H1K. A process for increasing the peak current of a tunnel diode comprises passing a current in the forward direction through the diode while monitoring its current-voltage characteristic and increasing the forward current until an initial increase in the peak current is observed. As shown, Fig. 4, a tunnel diode 4 is produced by alloying a dot 3 comprising an alloy of indium, copper, selenium, tellurium and sulphur to the surface of a wafer 2 of gallium arsenide doped with zinc. The device, is chemically etched to reduce the junction to the desired diameter and is then connected in the circuit shown. A forward current supplied by source 13 is switched through diode 4 by an electronic switch 9 operating at 100 kc/s. with a 10: 1 duty cycle. During the part of the cycle in which source 13 is disconnected a curve tracer 10a is connected to diode 4 and the currentvoltage characteristic displayed on a CRO 12. The doping levels are chosen so that initially the diode does not exhibit a negative resistance characteristic. The forward current supplied to the device is slowly increased until a peak appears in the characteristic displayed and is then held constant. The value of the peak current continues to increase and the process is terminated when the peak current reaches a value about 2% lower than its maximum value. In use the peak current of the diode slowly increases to its maximum value and then decreases, the end of the useful life being when the peak current is reduced to a value about 2 % lower than the maximum value. The desired value of peak current of the diode may be produced by an electrolytic etching process monitored using a curve tracer as before. In a second embodiment, Fig. 11, a tunnel diode is manufactured by pyrolytically depositing a layer 21 of silicon dioxide on the surface of a wafer 2 of gallium arsenide. The surface is masked by placing the end of a rod in contact with the oxide layer and applying a layer 22 of resist material. The wafer is chemically etched to dissolve the rod and the oxide layer beneath it to form a small window. Alternatively the window can be etched in the oxide layer using a photo-resist method. A dot 3 of donor material is placed over the window and alloyed to the wafer. The device is then electrically treated as previously described, the etching steps being omitted.

公开(公告)号：CA924823A

公开(公告)日：1973-04-17

申请号：CA97531

申请日：1970-11-06

Applicant: IBM

Inventor： DEWITT D

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L27/00

Abstract: 1304246 Transistors INTERNATIONAL BUSINESS MACHINES CORP 20 Oct 1970 [10 Nov 1969] 49655/70 Heading H1K A transistor is made as part of an integrated circuit structure by forming a sub-collector region in a restricted part of the surface of a semi-conductor layer of the opposite type, depositing an epitaxial layer of the same type thereon into which the region extends by outdiffusion, forming in the layer over part of the sub-collector a pedestal region extending down to the sub-collector, depositing a further epitaxial layer of the same type into which the pedestal region extends by outdiffusion and then forming in this layer, a base zone extending down to the pedestal region extension, and within that an emitter region. In the embodiment an N+ sub-collector is first formed in a P-wafer by masked diffusion and an N-epitaxial layer deposited over it. In successive masked diffusion steps P-type isolation walls and two upward extensions of the sub-collector are formed. After removal of masking a second N-epitaxial layer is grown with simultaneous outdiffusion of the walls 114 and upward extensions 117, 118, to yield the configuration shown in Fig. 9. In subsequent diffusion steps from the upper surface of this layer the walls and extension 18 are further extended to the surface, the base zone formed in one or two stages and the emitter zone formed within the base to give the structure shown in Fig. 11.

公开(公告)号：SE352783B

公开(公告)日：1973-01-08

申请号：SE1517770

申请日：1970-11-10

Applicant: IBM

Inventor： DEWITT D

IPC: H01L21/331 ,  H01L29/73 ,  H01L21/74 ,  H01L27/00 ,  H01L19/00

Abstract: 1304246 Transistors INTERNATIONAL BUSINESS MACHINES CORP 20 Oct 1970 [10 Nov 1969] 49655/70 Heading H1K A transistor is made as part of an integrated circuit structure by forming a sub-collector region in a restricted part of the surface of a semi-conductor layer of the opposite type, depositing an epitaxial layer of the same type thereon into which the region extends by outdiffusion, forming in the layer over part of the sub-collector a pedestal region extending down to the sub-collector, depositing a further epitaxial layer of the same type into which the pedestal region extends by outdiffusion and then forming in this layer, a base zone extending down to the pedestal region extension, and within that an emitter region. In the embodiment an N+ sub-collector is first formed in a P-wafer by masked diffusion and an N-epitaxial layer deposited over it. In successive masked diffusion steps P-type isolation walls and two upward extensions of the sub-collector are formed. After removal of masking a second N-epitaxial layer is grown with simultaneous outdiffusion of the walls 114 and upward extensions 117, 118, to yield the configuration shown in Fig. 9. In subsequent diffusion steps from the upper surface of this layer the walls and extension 18 are further extended to the surface, the base zone formed in one or two stages and the emitter zone formed within the base to give the structure shown in Fig. 11.

公开(公告)号：BE758682A

公开(公告)日：1971-05-10

申请号：BE758682D

Applicant: IBM

Inventor： DEWITT D

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L27/00 ,  H01L

Abstract: 1304246 Transistors INTERNATIONAL BUSINESS MACHINES CORP 20 Oct 1970 [10 Nov 1969] 49655/70 Heading H1K A transistor is made as part of an integrated circuit structure by forming a sub-collector region in a restricted part of the surface of a semi-conductor layer of the opposite type, depositing an epitaxial layer of the same type thereon into which the region extends by outdiffusion, forming in the layer over part of the sub-collector a pedestal region extending down to the sub-collector, depositing a further epitaxial layer of the same type into which the pedestal region extends by outdiffusion and then forming in this layer, a base zone extending down to the pedestal region extension, and within that an emitter region. In the embodiment an N+ sub-collector is first formed in a P-wafer by masked diffusion and an N-epitaxial layer deposited over it. In successive masked diffusion steps P-type isolation walls and two upward extensions of the sub-collector are formed. After removal of masking a second N-epitaxial layer is grown with simultaneous outdiffusion of the walls 114 and upward extensions 117, 118, to yield the configuration shown in Fig. 9. In subsequent diffusion steps from the upper surface of this layer the walls and extension 18 are further extended to the surface, the base zone formed in one or two stages and the emitter zone formed within the base to give the structure shown in Fig. 11.