公开(公告)号：SE323436B

公开(公告)日：1970-05-04

申请号：SE832367

申请日：1967-06-13

Applicant: IBM

Inventor： PALFI T ,  BUTLER J ,  IM S

IPC: H01L23/473 ,  H05K7/20

Abstract: 1,178,566. Circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORP. 27 April, 1967 [13 June, 1966], No. 19418/67. Heading H1R. In a circuit module in which the electronic circuit devices are each positioned in an aperture of a first circuit board and are interconnected with this board and a second circuit board positioned adjacent one face of the first board, the devices are cooled by means positioned adjacent the other face of the first board. As shown in the opened-out arrangement of Fig. 1A a metal cooling plate 16 is provided with a plurality of pedestals 20 each of which supports a monolithic circuit chip 22, 24 and each pedestal and its associated chip nest within an aperture in multilayer printed circuit board 18 so that the upper face of the chip 22 is coplanar with the upper face of circuit board 18. Recessed contact sockets 30, 32, 34 are disposed on the surface of board 18 and are interconnected with chip 22 via signal conductors 36. A plurality of shorter interconnecting conductors 38 provide power interconnections between the various conducting layers of circuit board 18 and chip 22, Fig. 2 (not shown). Recessed contact sockets 40 disposed about the edge of board 18 mate with power studs 50 of lower board 14 which comprises a multilayer circuit board 42, a stiffener plate 44 and a plurality of interconnecting pins 46. Board 42 has two signal interconnection layers 52, 54 with conductor lines running in the X- direction on layer 52 and in the Y-direction on layer 54 and a grounded shielding plane 56. Signal interconnections between the chips are provided through multilayer circuit board 42 which board has its circuits interconnected by through hole connections and connected to sockets 30, 32 &c. on board 18 by studs 48. A plurality of the modules 10 are plugged into a multilayer circuit board, Fig. 3 (not shown), and has a water-cooling manifold fitted directly over the modules so that the coolant fluid flows over the tops of cooling plates mounted on plates 16 and carries the heat away. The printed circuit board 18 includes an insulating layer having a high dielectric constant and board 14 includes an insulating layer having a low dielectric constant.

公开(公告)号：SE329213B

公开(公告)日：1970-10-05

申请号：SE791264

申请日：1964-06-29

Applicant: IBM

Inventor： BUTLER J ,  DEWITT D

IPC: H01L21/00 ,  H01L21/3063 ,  H01L29/00 ,  H01L7/56

Abstract: 1,060,755. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 27; 1964 [June 28, 1963], No. 21924/64. Heading H1K. A process for increasing the peak current of a tunnel diode comprises passing a current in the forward direction through the diode while monitoring its current-voltage characteristic and increasing the forward current until an initial increase in the peak current is observed. As shown, Fig. 4, a tunnel diode 4 is produced by alloying a dot 3 comprising an alloy of indium, copper, selenium, tellurium and sulphur to the surface of a wafer 2 of gallium arsenide doped with zinc. The device, is chemically etched to reduce the junction to the desired diameter and is then connected in the circuit shown. A forward current supplied by source 13 is switched through diode 4 by an electronic switch 9 operating at 100 kc/s. with a 10: 1 duty cycle. During the part of the cycle in which source 13 is disconnected a curve tracer 10a is connected to diode 4 and the currentvoltage characteristic displayed on a CRO 12. The doping levels are chosen so that initially the diode does not exhibit a negative resistance characteristic. The forward current supplied to the device is slowly increased until a peak appears in the characteristic displayed and is then held constant. The value of the peak current continues to increase and the process is terminated when the peak current reaches a value about 2% lower than its maximum value. In use the peak current of the diode slowly increases to its maximum value and then decreases, the end of the useful life being when the peak current is reduced to a value about 2 % lower than the maximum value. The desired value of peak current of the diode may be produced by an electrolytic etching process monitored using a curve tracer as before. In a second embodiment, Fig. 11, a tunnel diode is manufactured by pyrolytically depositing a layer 21 of silicon dioxide on the surface of a wafer 2 of gallium arsenide. The surface is masked by placing the end of a rod in contact with the oxide layer and applying a layer 22 of resist material. The wafer is chemically etched to dissolve the rod and the oxide layer beneath it to form a small window. Alternatively the window can be etched in the oxide layer using a photo-resist method. A dot 3 of donor material is placed over the window and alloyed to the wafer. The device is then electrically treated as previously described, the etching steps being omitted.