公开(公告)号：JP2003242775A

公开(公告)日：2003-08-29

申请号：JP2003056757

申请日：2003-03-04

Applicant: IBM

Inventor： JI BRIAN ,  KIRIHATA TOSHIAKI ,  DIMITRI NETIS

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To provide a method for activating hierarchically word lines. SOLUTION: A memory structure comprises a plurality of banks (each bank comprises a plurality of blocks), a plurality of timing critical address lines (the number of critical address lines is equal to the number of banks) connected to all of the blocks in respective ones of the blocks, and a plurality of dedicated address lines connected to respective ones of the blocks. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000251471A

公开(公告)日：2000-09-14

申请号：JP2000046381

申请日：2000-02-23

Applicant: IBM

Inventor： JI BRIAN ,  KIRIHATA TOSHIAKI ,  DIMITRI NETIS

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To activate a word line in a hierarchical form by equalizing the number of timing-critical address lines to the number of banks, and connecting plural exclusive address lines to respective one of each block. SOLUTION: After a first bank is decoded using a timing signal of a signal line 300, a timing signal of the signal line 300 is transferred, a single memory block 330 is decoded in the bank, lastly, a single word line WL is activated, and the third decoding is performed by a shared row decoder/word line driver 61. At the beginning, a pre-decoded address signal of the signal line 300 including timing information is used at a first level of hierarchical decoding, after a single bank of a unit is activated, an address signal in the signal line 300 is multiplexed with other addresses pre-recorded statically in a signal line 310 having possibility for continuous variation independently of a bank address.