公开(公告)号：WO2004053922A3

公开(公告)日：2004-09-10

申请号：PCT/GB0305265

申请日：2003-12-02

Applicant: IBM ,  IBM UK

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles

Abstract translation: 一种等离子体蚀刻系统，其具有带磁体的晶圆吸盘，该磁体在晶圆上施加磁场以将晶圆从带电粒子屏蔽。 磁场与晶圆平行，在晶圆表面附近最强。 磁场可以是直的，也可以是圆形的。 在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，并且离子通过静电排斥偏转。 允许中性物质通过磁场，并与晶圆碰撞。 中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。 而且，磁场可以保护晶片避免设计成从腔室表面清洗不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻

公开(公告)号：JP2010251799A

公开(公告)日：2010-11-04

申请号：JP2010167117

申请日：2010-07-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/304

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: PROBLEM TO BE SOLVED: To provide a plasma etching system having a wafer chuck including a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles.
SOLUTION: The magnetic field is parallel to the wafer, and the intensity thereof is highest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer is positively charged, and ions are deflected by electrostatic repulsion. Neutral chemical species are allowed to pass through the magnetic field, and collide with the wafer. Neutral chemical species generally provide higher isotropic and material-selective etching than charged particles, so that this magnetic field tends to increase etching isotropy and material selectivity. The magnetic field can protect the wafer from seasoning processes designed to remove unwanted films from the chamber surface because seasoning processes generally rely on etching by charged particles.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有晶片卡盘的等离子体蚀刻系统，该晶片卡盘包括在晶片上施加磁场以使晶片免受带电粒子的磁体。

解决方案：磁场平行于晶片，其强度在晶片表面附近最高。 磁场可以是直的或圆形的。 在操作中，电子通过洛仑兹力从晶片偏转，晶片带正电，离子被静电排斥偏转。 允许中性化学物质通过磁场，并与晶片碰撞。 中性化学物质通常提供比带电粒子更高的各向同性和材料选择性蚀刻，使得该磁场倾向于增加蚀刻各向同性和材料选择性。 磁场可以保护晶片免受设计用于从腔室表面去除不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：JP2003242775A

公开(公告)日：2003-08-29

申请号：JP2003056757

申请日：2003-03-04

Applicant: IBM

Inventor： JI BRIAN ,  KIRIHATA TOSHIAKI ,  DIMITRI NETIS

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To provide a method for activating hierarchically word lines. SOLUTION: A memory structure comprises a plurality of banks (each bank comprises a plurality of blocks), a plurality of timing critical address lines (the number of critical address lines is equal to the number of banks) connected to all of the blocks in respective ones of the blocks, and a plurality of dedicated address lines connected to respective ones of the blocks. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000251471A

公开(公告)日：2000-09-14

申请号：JP2000046381

申请日：2000-02-23

Applicant: IBM

Inventor： JI BRIAN ,  KIRIHATA TOSHIAKI ,  DIMITRI NETIS

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To activate a word line in a hierarchical form by equalizing the number of timing-critical address lines to the number of banks, and connecting plural exclusive address lines to respective one of each block. SOLUTION: After a first bank is decoded using a timing signal of a signal line 300, a timing signal of the signal line 300 is transferred, a single memory block 330 is decoded in the bank, lastly, a single word line WL is activated, and the third decoding is performed by a shared row decoder/word line driver 61. At the beginning, a pre-decoded address signal of the signal line 300 including timing information is used at a first level of hierarchical decoding, after a single bank of a unit is activated, an address signal in the signal line 300 is multiplexed with other addresses pre-recorded statically in a signal line 310 having possibility for continuous variation independently of a bank address.

公开(公告)号：AU2003285581A1

公开(公告)日：2004-06-30

申请号：AU2003285581

申请日：2003-12-02

Applicant: IBM

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.

公开(公告)号：DE60035630D1

公开(公告)日：2007-09-06

申请号：DE60035630

申请日：2000-01-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

公开(公告)号：DE60035630T2

公开(公告)日：2008-02-07

申请号：DE60035630

申请日：2000-01-22

Applicant: IBM ,  QIMONDA NORTH AMERICA CORP

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.