公开(公告)号：US3892606A

公开(公告)日：1975-07-01

申请号：US37442573

申请日：1973-06-28

Applicant: IBM

Inventor： CHAPPELOW RONALD E ,  DONEY DONALD A ,  DOULIN JOSEPH ,  LIN PAUL T ,  SCHIAVONE FRANK A

IPC: H01L29/78 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/00 ,  H01L7/50

CPC classification number: H01L21/00 ,  H01L21/30604 ,  H01L21/32134 ,  H01L29/00 ,  Y10S148/041 ,  Y10S148/042 ,  Y10S148/053 ,  Y10S148/067 ,  Y10S148/122

Abstract: A method for forming contoured electrodes of polycrystalline silicon by grading the concentration of dopant diffused into the silicon layers during the deposition process. Upon etching the silicon after deposition to form electrodes, e.g., the gate electrode of a field effect transistor, the electrode is desirably tapered. Conductive and insulator layers subsequently deposited atop the tapered electrode are less subject to cracking and lifting off than standard electrodes.

Abstract translation: 一种用于通过在沉积工艺期间对扩散到硅层中的掺杂剂的浓度进行分级来形成多晶硅的轮廓电极的方法。 在沉积之后蚀刻硅以形成电极，例如场效应晶体管的栅电极，期望电极是锥形的。 随后沉积在锥形电极顶部的导电层和绝缘体层比标准电极更少受到破裂和剥离。

公开(公告)号：DE2422138A1

公开(公告)日：1975-01-23

申请号：DE2422138

申请日：1974-05-08

Applicant: IBM

Inventor： CHAPPELOW RONALD EDWARD ,  DONEY DONALD ALDEN ,  DOULIN JOSEPH ,  LIN PAUL TACHANG

IPC: H01L29/78 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/00 ,  H01L21/72

Abstract: A method for forming contoured electrodes of polycrystalline silicon by grading the concentration of dopant diffused into the silicon layers during the deposition process. Upon etching the silicon after deposition to form electrodes, e.g., the gate electrode of a field effect transistor, the electrode is desirably tapered. Conductive and insulator layers subsequently deposited atop the tapered electrode are less subject to cracking and lifting off than standard electrodes.

公开(公告)号：CA1009768A

公开(公告)日：1977-05-03

申请号：CA201572

申请日：1974-06-04

Applicant: IBM

Inventor： CHAPPELOW RONALD E ,  DONEY DONALD A ,  DOULIN JOSEPH ,  LIN PAUL T ,  SCHIAVONE FRANK A

IPC: H01L29/78 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/00

Abstract: A method for forming contoured electrodes of polycrystalline silicon by grading the concentration of dopant diffused into the silicon layers during the deposition process. Upon etching the silicon after deposition to form electrodes, e.g., the gate electrode of a field effect transistor, the electrode is desirably tapered. Conductive and insulator layers subsequently deposited atop the tapered electrode are less subject to cracking and lifting off than standard electrodes.