公开(公告)号：WO2004019192A3

公开(公告)日：2004-09-10

申请号：PCT/EP0308486

申请日：2003-07-10

Applicant: IBM ,  COMPANIE IBM FRANCE

Inventor： BURNS JEFFREY L ,  DRAKE ALAN J ,  GHOSHAL UTTAM SHYAMALINDU ,  NOWKA KEVIN J

IPC: H03K3/353 ,  H03B5/12 ,  H03K3/354 ,  H03K5/15 ,  G06F1/08

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03K3/354

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.

Abstract translation: 一种包括时钟发生器的系统和集成电路（芯片），其包括片上电感器并且使用负载的固有电容来产生正弦时钟信号。 电感连接在电流源和反相开关之间。 开关的输出是基本上正弦信号，其直接连接到时钟驱动电路的至少一部分而没有中间缓冲。 在优选实施例中，时钟发生器是双相设计，其包括一对交叉耦合MOSFET，一对固态片上电感器和电流源。 每个片上电感器连接在MOSFET之一的电流源和漏极之间。 时钟发生器的输出被直接提供给芯片上至少一部分时钟驱动电路的时钟输入。 在该实施例中，时钟发生器输出信号的频率主要由电感元件的电感和时钟驱动电路的电容决定。 该设计消除了在时钟发生器本身中并入不同的电容器元件并产生时钟发生器的需要，其中大部分功率在发电机的感应元件和负载的电容元件之间振荡，从而减少由 当前来源。

公开(公告)号：DE60318724D1

公开(公告)日：2008-03-06

申请号：DE60318724

申请日：2003-07-10

Applicant: IBM

Inventor： BURNS JEFFREY L ,  DRAKE ALAN J ,  GHOSHAL UTTAM SHYAMALINDU ,  NOWKA KEVIN J

IPC: G06F1/08 ,  H03K3/353 ,  H03B5/12 ,  H03K3/354 ,  H03K5/15

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.

公开(公告)号：AU2003250200A8

公开(公告)日：2004-03-11

申请号：AU2003250200

申请日：2003-07-10

Applicant: IBM

Inventor： BURNS JEFFREY L ,  GHOSHAL UTTAM SHYAMALINDU ,  DRAKE ALAN J ,  NOWKA KEVIN J

IPC: H03K3/353 ,  H03B5/12 ,  H03K3/354 ,  H03K5/15 ,  G06F1/08

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.

公开(公告)号：DE60318724T2

公开(公告)日：2009-01-02

申请号：DE60318724

申请日：2003-07-10

Applicant: IBM

Inventor： BURNS JEFFREY L ,  DRAKE ALAN J ,  GHOSHAL UTTAM SHYAMALINDU ,  NOWKA KEVIN J

IPC: G06F1/08 ,  H03K3/353 ,  H03B5/12 ,  H03K3/354 ,  H03K5/15

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.

公开(公告)号：AU2003250200A1

公开(公告)日：2004-03-11

申请号：AU2003250200

申请日：2003-07-10

Applicant: IBM

Inventor： GHOSHAL UTTAM SHYAMALINDU ,  NOWKA KEVIN J ,  BURNS JEFFREY L ,  DRAKE ALAN J

IPC: H03K3/353 ,  H03B5/12 ,  H03K3/354 ,  H03K5/15 ,  G06F1/04

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.