公开(公告)号：DE1774571A1

公开(公告)日：1971-12-02

申请号：DE1774571

申请日：1968-07-18

Applicant: IBM

Inventor： COCKE JOHN ,  VISVALD FREIMAN CHARLES ,  EDWARD HOMAN MERLE

IPC: G06F7/52 ,  G06F7/535

Abstract: 1,177,608. Dividers; data storage. INTERNATIONAL BUSINESS MACHINES CORP 20 June, 1968 [19 July, 1967], No. 29364/68. Headings G4A and G4C. Division of a multi-order dividend by a predetermined divisor is done by concurrently generating a plurality of intermediate remainders relating to respective orders, combining each dividend order with the next higher order intermediate remainder and dividing the result by the predetermined divisor. Figs. 12A, 12B show division of an octal number by a fixed divisor equal to 3. Each quotient digit is generated in a respective circuit 130, 132 which divides its input by 3 and discards the remainder. In the case of the highest order digit, this input is the highest order dividend digit (circuit 130) but in the other cases (circuits 132) it is a two-digit octal number formed by the corresponding dividend digit (as low-order digit) concatenated with a one-digit intermediate remainder obtained from higher order dividend digits as shown using circuits 134, 126, 128. Each circuit 134 casts out threes from a corresponding dividend digit. Each circuit 126 subtracts its left input from its upper input and casts out threes from the result (i.e. is a modulo-3 subtractor), and each circuit 128 adds its two inputs and casts out threes from the result (i.e. is a modulo-3 adder). Each octal digit is binary-coded so the dividend is also binary. Similar circuits are described for a radix 10, divisor 7 division, radix 8, divisor 7, radix 10, divisor 5, and radix 16, divisor 5 (the 16 is binary-coded so the dividend is also binary radix). Each circuit corresponding to 126, 128 in effect multiplies its left input by (R modulo D) Y modulo D, the least positive or negative value being used, where D is the divisor, R the radix and Y the number of orders the input has traversed from its generation point. The resulting product is added to the upper input and the result, modulo the divisor, is the circuit output. In some embodiments, the quantity "R modulo D" is one in which case the multiplication stage is dispensed with, or even zero in which case circuits corresponding to 126, 128 are completely absent. The above embodiments may be preceded by a shift register permitting a preliminary further division by a power of 2 by shifting. Data storage.-In a memory system having a plurality of data words per memory word, the divider above may be used to divide the data word address, the quotient being used to address the memory word and the remainder to select the data word from the memory word.