公开(公告)号：DE1474046A1

公开(公告)日：1971-04-08

申请号：DE1474046

申请日：1964-10-23

Applicant: IBM

Inventor： TIENWEN CHIEN ROBERT ,  VISVALD FREIMAN CHARLES

IPC: G06F17/30 ,  G06F9/00

Abstract: 1,051,786. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 30, 1964 [Oct. 23. 1963]. No. 39741/64. Headings G4A and G4C. A data item is stored at an address depending on the remainder from a division of a key identifying the item by an m-th order polynomial, m being less than the number of digits in each key, the series of digits of a key belonging to an algebraic ring with a unit element to which the coefficients of the polynomial also belong. Referring to Fig. 1, data on lines 18b from an information processor 12 can be stored in a file memory 16 together with a key identifying it (on lines 18a) at that unused location whose address is closest to, but not less than, an address derived from the key in a circuit 14. To retrieve data, the key is applied to circuit 14 and the resulting address used to address memory 16 as before. The keys stored in the addressed location and subsequent locations are compared in turn with the required key present on lines 18a, and the data read out on to lines 18b on a match being obtained. The key-to-address transformation circuit 14 receives the key serially on line 26, augments (if necessary) its length to an integral multiple of m bits, performs the division referred to and produces the remainder (the address) on line 28. The first and last bits of the key on line 26 are indicated by first and second pulses L on line 27 to control circuit 20. The first of these produces an output from modulo-2 adder 72 which via an (m- 1) bit delay 88 sets a flip-flop 112 to enable AND-gate 42 in circuit 14 (see Fig. 1) and which also resets modulo-m counter 92 which counts bit-timing signals on line CP. The second pulse L triggers (m - 1)-bit astable multivibrator 78 which thereupon enables AND-gate 98 for an interval of (m - 1) bit times. The first output from modulo-m counter 92 during this interval resets flip-flop 112, thus (by a signal on line 32) shifting the contents of delay line 38 an m-bit shift register 62, the output of which (in parallel) is used for addressing the memory 16. If a new first-bit signal L arrives while flip-flop 112 is still set, an alarm signal is produced on line 66. The file memory 16 may consist of microfilm or magnetic tape. If all keys are of the same (appropriate) length, units 78. 92, 98 may be dispensed with and line 76 connected directly to line 104.

公开(公告)号：DE1774571A1

公开(公告)日：1971-12-02

申请号：DE1774571

申请日：1968-07-18

Applicant: IBM

Inventor： COCKE JOHN ,  VISVALD FREIMAN CHARLES ,  EDWARD HOMAN MERLE

IPC: G06F7/52 ,  G06F7/535

Abstract: 1,177,608. Dividers; data storage. INTERNATIONAL BUSINESS MACHINES CORP 20 June, 1968 [19 July, 1967], No. 29364/68. Headings G4A and G4C. Division of a multi-order dividend by a predetermined divisor is done by concurrently generating a plurality of intermediate remainders relating to respective orders, combining each dividend order with the next higher order intermediate remainder and dividing the result by the predetermined divisor. Figs. 12A, 12B show division of an octal number by a fixed divisor equal to 3. Each quotient digit is generated in a respective circuit 130, 132 which divides its input by 3 and discards the remainder. In the case of the highest order digit, this input is the highest order dividend digit (circuit 130) but in the other cases (circuits 132) it is a two-digit octal number formed by the corresponding dividend digit (as low-order digit) concatenated with a one-digit intermediate remainder obtained from higher order dividend digits as shown using circuits 134, 126, 128. Each circuit 134 casts out threes from a corresponding dividend digit. Each circuit 126 subtracts its left input from its upper input and casts out threes from the result (i.e. is a modulo-3 subtractor), and each circuit 128 adds its two inputs and casts out threes from the result (i.e. is a modulo-3 adder). Each octal digit is binary-coded so the dividend is also binary. Similar circuits are described for a radix 10, divisor 7 division, radix 8, divisor 7, radix 10, divisor 5, and radix 16, divisor 5 (the 16 is binary-coded so the dividend is also binary radix). Each circuit corresponding to 126, 128 in effect multiplies its left input by (R modulo D) Y modulo D, the least positive or negative value being used, where D is the divisor, R the radix and Y the number of orders the input has traversed from its generation point. The resulting product is added to the upper input and the result, modulo the divisor, is the circuit output. In some embodiments, the quantity "R modulo D" is one in which case the multiplication stage is dispensed with, or even zero in which case circuits corresponding to 126, 128 are completely absent. The above embodiments may be preceded by a shift register permitting a preliminary further division by a power of 2 by shifting. Data storage.-In a memory system having a plurality of data words per memory word, the divider above may be used to divide the data word address, the quotient being used to address the memory word and the remainder to select the data word from the memory word.