公开(公告)号：DE2132560A1

公开(公告)日：1972-01-05

申请号：DE2132560

申请日：1971-06-30

Applicant: IBM

Inventor： TZE HO IRVING ,  EDWARD HOWELL PETER ,  JEN TEH-SEN

IPC: G11C19/18 ,  G11C19/28 ,  G11C19/00

Abstract: 1345604 Semi-conductor data storage cell INTERNATIONAL BUSINESS MACHINES CORP 27 May 1971 [30 June 1970] 17441/71 Heading H3T [Also in Division G4] A capacitor storage cell C28, C33, T44, T46 has its stored data refreshed or maintained by a transistor 50 cross-coupled with T46 (Fig. 1). C28 is charged by a pulse 16 (Fig. 1A) at terminal 14 via R22, D24 and line 26, and discharged or not by T44 if the data input 10 is high or low respectively, when a negative pulse 56 occurs at T44 emitter 30; then C33 is charged by pulse 32 at 30 via R36, D38 and discharged or not by T46 when a negative pulse 52 occurs at T46 emitter 14 depending upon the stored voltage on C28. To regenerate the information stored to allow for leakage, a similar cycle of pulses is applied at times t 5 -t 8 but instead of T44 discharging C28 in dependence on the input, T50 is biased by a pulse 50 at 58 to discharge C28 or not according to the already stored level on C33. The transistor 50 may be replaced by a cross-coupled pair (T128, 130, Fig. 2, not shown) and in this case stored, information is maintained merely by a constantly applied negative level - V at their commoned emitters (134). A shift register (Fig. 3, not shown) has a plurality of these cells (156-m) in each row (150-n).