公开(公告)号：JP2000003295A

公开(公告)日：2000-01-07

申请号：JP9643199

申请日：1999-04-02

Applicant: IBM

Inventor： FRANK ELLIOTT LEVIN ,  ROY STUART MOORE ,  CHARLES PHILIP ROSS ,  EDWARD HUGH WELBONE

IPC: G06F9/38 ,  G06F11/34

Abstract: PROBLEM TO BE SOLVED: To provide a method which can progress and monitor an instruction in a processor by preparing a circuit, etc., that can operate to transfer a 1st or 2nd reason code to a 3rd stage by means of a 1st or 2nd execution unit serving as a 2nd stage. SOLUTION: If a dispatch unit serving as a 1st stage stops its operation and cannot dispatch the instructions, a 1st execution unit serving as a 2nd stage receives no Job in a step 801. Then the processing proceeds to a step 803 to decide whether the 1st execution unit can produce its result. Therefore, the 1st execution unit carries out a division operation that requires plural cycles and can produce its result as soon as the division operation is over. Then in a step 804, the 1st execution unit transfers the result of the division operation (e.g. a 1st reason code) to an end unit serving as a 3rd stage.

公开(公告)号：JPH10275099A

公开(公告)日：1998-10-13

申请号：JP4912798

申请日：1998-03-02

Applicant: IBM

Inventor： FRANK ELLIOTT LEVIN ,  CHARLES PHILIP ROSS ,  EDWARD HUGH WELBONE ,  JECK CHRIS RANDOLPH

IPC: G06F11/34

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive monitor which can improve the analysis capability of system performance in a wide range by adding a performance monitoring function to a peripheral device that is connected to a processor. SOLUTION: A system 80 includes a programmable circuit 802 which includes a performance monitoring function 50. The circuit 802 is connected to a CPU 10 via a bus 807, to a DMA controller 803 via a bus 809, to a memory controller 804 via a bus 808 and then to a bridge circuit 805 via a bus 811. The circuit 802 is used together with or in place of the CPU 10 in order to execute the performance monitoring analysis of a certain type by means of the function 50 included in the circuit 802. Thus, this performance monitor is applied to execution of the function 50 at the inside of the CPU 10 or the circuit 802 or for the combination of the CPU 10 and the circuit 802.