公开(公告)号：DE1524142A1

公开(公告)日：1971-08-19

申请号：DE1524142

申请日：1966-03-30

Applicant: IBM

Inventor： JOHN HASBROUCK LEO ,  RICHARD HOLLERAN CHARLES ,  EDWARD KING LEWIS ,  PAUL WISSICK WILLIAM

IPC: G06F13/12 ,  G06F13/18 ,  G06F15/78 ,  G06F9/18

Abstract: 1,138,671. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 31 March, 1966 [5 April, 1965], No. 14305/66. Heading G4A. In a data processing system, a storage access request from an input/output channel is given priority over one from a processing unit occurring in the same cycle if the storage is busy servicing another request but if it is not busy the processing unit request has priority. Selection circuits (Fig. 9).-Any one of seven channels (input, output, maintenance) may request access to storage (for data transfer either way) by setting corresponding service latches, in CH PRI, the lowest numbered of the set latches giving rise to a corresponding priority bit, in CH PRI, which sets a latch in BFR to prevent further setting of the service latches and to pulse a delay network DLY. The delay network sends a data request signal and a response signal to the channel specified by the priority bit, DATA REQ, BCU RSP, and sets a channel request latch CH REQ. A bit in a storage address supplied by the channel specifies whether an even or odd storage section of one of two frames is required and provided it is not already busy, a channel select even or odd signal is produced CH E/O. If either of these signals is produced, a signal blocking access to storage by a CPU (i.e. central processing unit) is produced GT CH NOT CPU BLK. The CPU may access an even or odd section of storage provided it is not busy and the blocking signal is absent, by setting a CPU request latch CPU REQ and producing a CPU select even or odd signal CPU E/O. A CPU request has priority over a channel request occurring in the same cycle if the storage is not busy when the rerequests occur, but if it is busy the channel is given priority when the storage becomes free. A storage address register has a (physically remote) duplicate section DUP SAR for the bit specifying even or odd, and also for a bit specifying which of the frames is required A branch or interrupt rendering unnecessary CPU storage request already made resets th CPU request latch CPU REQ without the access being made. Storage, input circuits (Fig. 10).-A storage address, supplied by either the CPU or a channel (whichever has access), comprises 24 address bits plus a parity bit for each 8 address bits. One address bit selects a storage frame, one selects an even or odd section within it, 14 select a word, 3 select a byte, and 5 are not used (unless extra storage is provided) except that one of the 5 is set to " one " to specify fetching of data from the panel (console). An " invalid address " signal is produced INV ADR if address bits which should not be used are used, or if the odd or even half of a storage frame selected is out of service (indicated by manual switches controlling " ready " lines). An address check signal is produced SAB ADR CHK as a result of a parity check on the address. If the address is invalid and a panel switch is not set or the address has incorrect parity, or if a fetch from the panel is indicated by the address and a panel switch is set, storage access is cancelled and the storage replaced by the panel as a source of data CANC PKF. Two new parity bits for the 14 address bits used for word selection are derived from the full address and the parity bits supplied with it PAR ADJ. Provision is made for comparing the full address with one set up on panel keys ADR COMP. So called " marks " are provided MARKS for selecting bytes in a storage word (e.g. for alteration before restoring), bytes being specifiable individually by a channel (when in control) or during variable field length operations by the CPU, but only in pairs during other CPU operations. A mark parity bit is provided and may be updated during variable field length operations as successive marks are provided. A block of storage may be accessed only if a 4-bit protection key corresponding to it agrees with a key supplied IN KEYS by the channel or CPU, whichever is in control, or if either key is 0000. Each key from a channel or CPU has a parity bit. The CPU key is selected from one of two sources (instruction register and programme status word) and a parity bit for it is derived from a parity bit relating to it and 4 other bits, and said other bits IN KEYS. Storage output circuits (Fig. 11).-Two " tracking " triggers X/Y-W/Z keep track of which accessed data belongs to which request, partially controlling registers X REG, Y REG to indicate the destination of the data and routing various error indications (protection, address parity) to the CPU or channel as appropriate SAP, STR ADR CHK. Whenever neither an even nor an odd section of storage is busy, the " tracking " triggers are checked X/Y-W/Z CHK. In the case of an error signal from this, or from a data parity check in a CPU store (as distinct from fetch) access STR DATA CHK, or from an address parity check in a CPU access STR ADR CHK, a stop clock signal is produced BCU STP CLK. Protection keys from either frame may be accessed OUT KEYS. As mentioned above, data from panel keys may take the place of data from storage, in an output buffer SBOL.

公开(公告)号：DE1299145B

公开(公告)日：1969-07-10

申请号：DEJ0033462

申请日：1967-04-18

Applicant: IBM

Inventor： JOSEPH ANNUNZIATA EUGENE ,  SIDNEY JAMES ROBERT ,  EDWARD KING LEWIS ,  BRUCE PIERCE EDWIN

IPC: G06F13/12 ,  G06F7/06

Abstract: 1,137,812. Computer input/output control. INTERNATIONAL BUSINESS MACHINES CORP. 8 March, 1967 [19 April, 1966], No. 10808/67. Heading G4A. A data processing system comprises a CPU (central processing unit), main storage and a plurality of peripheral units, the peripheral units being grouped under the control of subcontrol units controlled in turn by a common control unit associated with enough local storage to contain control words for each peripheral unit and arranged so that data transfer between a peripheral unit and main storage can be established by execution of an instruction by the CPU causing the common control unit to retrieve a unit control word from main storage and put it in the local storage, the control word being updated as transfer proceeds. A system comprising CPU and main core storage has input/output channels, each as follows. Input/output units are connected in groups to control units which are connected in groups to sub-channels. Four of the subchannels relate to high-speed input/output units, e.g. magnetic tape units, and operate in burst mode i.e. transfer a complete multi-byte message at each link-up, whereas a fifth subchannel relates to low-speed input/output units, e.g. card readers and punches, and operates in multiplex mode i.e. transfers one byte per link-up. The five sub-channels are connected to a common control unit having a 1024-word local storage and this control unit is connected to the CPU and main storage. Priority arrangements (not described) are in operation at each level of the communication system. Burst mode transfer.-An input/output instruction specifies the channel and input/output unit and causes the common control unit of the channel to access a channel address word from main storage. The common control unit then accesses a channel command word from main storage at an address specified by the channel address word. The channel command word specifies the operation to be performed by the input/output unit, the first main storage address (word and byte) to deliver or receive transferred data and the number of bytes to be transferred. The channel address word has its address field incremented by 8 bytes (one word), to specify the next channel command word when needed, and is then stored in the local storage as a first unit control word for the particular input/output unit concerned. The channel command word (with its operation field replaced by conventional tags from the channel address word) is also stored in the local storage as a second unit control word. The input/output unit recognizes its address sent from the common control unit and sends its address back for a check comparison. In the case of agreement, the message is transmitted between main storage and the common control unit, serially by 8-byte word, and between the common control unit and the input-output unit serially by byte, the unit control words being updated as appropriate. Multiplex mode transfer.-Since only one byte is transferred per link-up in this mode, the mode differs from burst mode as follows. Two unit control words are stored in the local storage under programme control as before. Thereafter, whenever the input/output unit is ready to supply or receive a message byte it sends its address to the common control unit to access its second unit control word from the local storage. The message is transferred serially by word between the main storage and the common control unit as before, and between additions or removals of bytes to or from the current message word in the common control unit, this message word is stored as a third unit "control" word in the local storage. A fourth unit control word in the local storage is constituted by the next channel command word prefetched from main storage. Interruption.-Apart from interruption for data transfer, the CPU can also be interrupted for other unspecified purposes by a channel, the common control unit thereof supplying to the main storage the address of the input/output unit involved and a channel status word partly constituted by the channel address word (updated) and partly by input/output unit status bits.

公开(公告)号：DE1524882A1

公开(公告)日：1970-11-26

申请号：DE1524882

申请日：1967-11-10

Applicant: IBM

Inventor： COCHRAN COOPER JAMES ,  EDWARD KING LEWIS ,  LOWE MACSORLEY OLIN ,  PAUL WISSICK WILLIAM

IPC: G06F12/08 ,  G06F13/18 ,  G11B13/00

Abstract: 1,193,720. Computers; storage. INTERNATIONAL BUSINESS MACHINES CORP. 9 Nov., 1967 [10 Nov., 1966], No. 50932/67. Headings G4A and G4C. In data processing apparatus, a priority circuit receives storage requests, and a bulk storage device includes means for generating a " device busy " signal followed by three further timing signals, a bulk storage bus rate control device being set to a first state in response to a storage request relating to a bulk storage device and being set to a second state in response to the first further timing signal, the first state causing generation of a signal to inhibit application of bulk storage requests to the priority circuit. The disclosures are essentially as in Specification 1,193,719 which is referred to.

公开(公告)号：DE1524179A1

公开(公告)日：1970-04-09

申请号：DE1524179

申请日：1966-12-13

Applicant: IBM

Inventor： EDWARD KING LEWIS ,  CLIFFORD HOSKINSON WILLIAM ,  JOSEPH ANNUNZIATA EUGENE

IPC: G06F12/04 ,  G06F13/12

Abstract: 1,155,849. Digital data stores. INTERNATIONAL BUSINESS MACHINES CORP. 1 Nov., 1966 [14 Dec. 1965], No. 48809/66. Heading G4C. A stored mask and a counter select byte positions in a multi-byte word store used for communication between a central processor and a byte channel. Data passes between a computer memory and input/output devices (e.g. magnetic drum, disc, tape or card reader) via a one-word assembly register 26 under control of a programmed channel command word (Fig. 1). Each data word has 8 bytes, each byte having 8 data bits and one parity bit. The channel command word supplies the word portion of an initial data address to a data word address register 15 to address the memory, and the byte portion of the address to preset a byte counter 17. It also supplies a count field to a count register 16, an 8-bit mask to a byte mask register 19, and a flag bit to a bit-register 18. Input to computer.-If the flag bit at 18 is 0, successive input bytes arriving at 28 are passed by AND gates 22 into respective byte positions of assembly register 26, the byte positions of the register used for this purpose being those corresponding to a bit 0 in the mask register 19, one bit position in the latter corresponding to each byte position in register 26. This is done by advancing the byte counter 17 from its preset value by means of a step generator 29 to mark successive output leads of the counter until the marked lead corresponds in position to a 0 in mask register 19 when a match decoder 33 (utilising exclusive-ors) sets a match trigger 31 to inhibit further counter advance. The mask register 19 and byte counter 17 enable the appropriate set of AND gates 22 to pass the input byte to the appropriate position of the assembly register 26. At the same time, a corresponding bit position of a mark B register 23 is set to 1. Then the input equipment resets the match trigger 31 to allow the byte counter 17 to advance further. The speed of the byte counter 17 is such that all bytes are allocated to some position in register 26. When byte counter 17 advances from 7 to 0, the count register 16 is decremented by 8, and the contents of the assembly register 26 and mark B register 23 are transferred to a buffer register 42 and a mark A register 43. The bytes of the storage word addressed by register 15, which correspond to 1 bits in the mark A register, are replaced by the corresponding bytes of the buffer register 42, the other bytes being rewritten unchanged. The address register 15 is incremented by one, and operations repeat until the count register 16 holds zero. However, if the flag bit at 18 is 1, one input byte corresponds to each byte position in assembly register 26 and those bytes corresponding to byte positions having a 1 in mask register 19 are discarded. This is achieved by causing each pulse from generator 29 to not only advance byte counter 17 but also, via AND 46, to set the match trigger 31, thereby inhibiting further counter advance until a byte has been supplied and the trigger 31 reset by the input equipment. Output from computer.-A word is read from the computer memory via buffer register 42 to assembly register 26. The byte counter 17 is advanced rapidly as in the first input mode, the flag bit at 18 being 0, until it reaches a 0 in the mask register 19 when the counter 17 is inhibited as in the first input mode. The byte counter 17 gates the corresponding byte in assembly register 26 to an output bus via AND gates 47. The output equipment then resets trigger 31 to allow the counter 17 to advance again. Otherwise, the output mode is like the first input mode.

公开(公告)号：DE1499206A1

公开(公告)日：1970-01-15

申请号：DE1499206

申请日：1965-04-06

Applicant: IBM

Inventor： EDWARD KING LEWIS ,  CLIFFORD HOSKINSON WILLIAM ,  JOSEPH ANNUZIATA EUGENE ,  WILLIAM WISE FRANCIS ,  BRUCE PIERCE EDWIN

IPC: G06F12/04 ,  G06F13/12 ,  G11B13/00

Abstract: 1,062,225. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 5, 1965 [April 6, 1964], No. 14261/65. Heading G4A. Multi-byte words of data are transferred between a computer store and a selected input/ output device via a word-sized first assembly register, each byte being entered as it arrives into a portion of the assembly register selected by a byte counter which is incremented by one after each such entry. A data address (DA) register specifies the memory word involved in the transfer and also has three bits to specify a byte within the word. Describing transfer to (core) memory, the three " byte " bits from the DA register are set into the byte counter to enter the first byte arriving into the appropriate section of the first assembly register. The byte counter is then incremented as successive bytes arrive until the last byte position of the first assembly register is filled, entry of each byte being accompanied by entry of a mark bit (1) into a corresponding position of a first mark register. The contents of the first assembly register and first mark register are passed to a second assembly register and a second mark register respectively to allow the first registers to continue operations while the second registers enter the data into store as follows. The memory word addressed by the DA register is read out and the bytes in the positions not having a 1 in the second mark register are read back, together with the bytes from the second assembly register having a 1 in the second mark register (Figs. 15A, 15B, not shown). The contents of a count (CT) register, initially specifying the number of bytes to be transferred, are added to the " byte " bits of the DA register and the result placed back in the CT register. As each word is transferred into memory, the CT register is decremented by 8 (the number of bytes per word), and the DA register incremented by one word position, in the same adder as used before. When the last word is being assembled, the transfer process is terminated when the CT register contents equal the byte counter contents plus one as determined by a comparator, the byte counter having a section continually storing the true count plus one for this purpose. A number of input/output channel units can time-share lines to the computer and each channel unit can scan a number of associated input/output control units in turn by means of a signal on a " select out " line. Each control unit may have a number of associated input/output devices (Fig. 1, not shown). Channel command words (Fig. 4, not shown) are used to control input/output operations (e.g. they set the DA and CT registers), being accessed from addresses placed in a command address (CA) register from a channel address word (Fig. 3, not shown) or from the adder after incrementation of the previous command address. The adder incorporates parity checking circuitry. Since a byte may arrive slightly before the channel command word specifying its allotment is accessed, each byte is placed in both halves of the assembly register (Fig. 16, not shown) until the required location is indicated when one of the occurrences of the byte(s) is deleted. Input/output devices mentioned are magnetic tape/drum/disc units, printers, card readers and punches, core memories, telegraph units, and typewriters. Byte counter.-Referring to Figs. 14A, 14B (not shown), this has three counting stages (975, 976, 977) and a parity check stage (981), the former being presettable over lines (978, 979, 980). Each stage (975, 976, 977, 981) has a corresponding look-ahead stage (975 1 , 976 1 , 977 1 , 9811) which store the count plus one (and parity bit). Setting stages (975 11 , 97611, 977 11 , 981 11 ) are associated with the look-ahead stages, store the same number thereas, and are used to advance the counting stages (975, 976, 977) on receipt of an advance pulse on a change line.