公开(公告)号：US3374472A

公开(公告)日：1968-03-19

申请号：US60925267

申请日：1967-01-13

Applicant: IBM

Inventor： WISSICK WILLIAM P ,  HASBROUCK LEO J ,  RICHARD HOLLERAN CHARLES ,  SMITH GORDON L

IPC: G06F3/023 ,  G06F3/048 ,  G06F11/00 ,  G06F13/42

CPC classification number: G06F11/0751 ,  G06F3/0489 ,  G06F11/00 ,  G06F11/002 ,  G06F13/4234

Abstract: 1,133,848. Computers. INTERNATIONAL BUSINESS MACHINES CORP. 4 April, 1966 [5 April, 1965], No. 14756/66. Heading G4A. In a data processing system, detection of a predetermined condition causes (a) cancellation of a storage access and (b) accessing of data from panel keys, neither of events (a) and (b) ever occurring without the other. Storage access requests from input/output channel units and a central processing unit are resolved on a priority basis and the selected unit supplies an address word. An invalid address signal is produced if any of the 5 or 6 (depending on the number of storage units used) highest order bits of the address word is 1, except when only the highest order bit of the 5 or 6 is 1 in conjunction with the set position of an enabling control panel key. The invalid address signal is also produced if the selected storage unit is manually switched out of system for maintenance or if its power supply has failed. The storage access (which will have already started) is cancelled in any of the following circumstances and data is obtained from panel keys instead: (a) if a parity check on the address word, which includes 3 parity bits, indicates error, (b) if the invalid address signal is present and a disabling panel key is not set, (c) if the highest order bit of the address word is 1 and the enabling key mentioned is set, (d) in various resetting situations: Since only part of the address word is actually used for addressing, the part which is used (i.e. the whole word less the bits which if equal to 1 could give an invalid address indication) are supplied to the store together with 2 new parity bits derived from the part and one of the original parity bits, a parity check occurring at the store. The whole address word is also compared against panel keys if a further panel key so commands.

公开(公告)号：US3376556A

公开(公告)日：1968-04-02

申请号：US60923967

申请日：1967-01-13

Applicant: IBM

Inventor： HASBROUCK LEO J ,  RICHARD HOLLERAN CHARLES ,  KING LEWIS E ,  WISSICK WILLIAM P

IPC: G06F13/12 ,  G06F13/18 ,  G06F15/78

CPC classification number: G06F13/18 ,  G06F13/122 ,  G06F15/78

公开(公告)号：DE1524142A1

公开(公告)日：1971-08-19

申请号：DE1524142

申请日：1966-03-30

Applicant: IBM

Inventor： JOHN HASBROUCK LEO ,  RICHARD HOLLERAN CHARLES ,  EDWARD KING LEWIS ,  PAUL WISSICK WILLIAM

IPC: G06F13/12 ,  G06F13/18 ,  G06F15/78 ,  G06F9/18

Abstract: 1,138,671. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 31 March, 1966 [5 April, 1965], No. 14305/66. Heading G4A. In a data processing system, a storage access request from an input/output channel is given priority over one from a processing unit occurring in the same cycle if the storage is busy servicing another request but if it is not busy the processing unit request has priority. Selection circuits (Fig. 9).-Any one of seven channels (input, output, maintenance) may request access to storage (for data transfer either way) by setting corresponding service latches, in CH PRI, the lowest numbered of the set latches giving rise to a corresponding priority bit, in CH PRI, which sets a latch in BFR to prevent further setting of the service latches and to pulse a delay network DLY. The delay network sends a data request signal and a response signal to the channel specified by the priority bit, DATA REQ, BCU RSP, and sets a channel request latch CH REQ. A bit in a storage address supplied by the channel specifies whether an even or odd storage section of one of two frames is required and provided it is not already busy, a channel select even or odd signal is produced CH E/O. If either of these signals is produced, a signal blocking access to storage by a CPU (i.e. central processing unit) is produced GT CH NOT CPU BLK. The CPU may access an even or odd section of storage provided it is not busy and the blocking signal is absent, by setting a CPU request latch CPU REQ and producing a CPU select even or odd signal CPU E/O. A CPU request has priority over a channel request occurring in the same cycle if the storage is not busy when the rerequests occur, but if it is busy the channel is given priority when the storage becomes free. A storage address register has a (physically remote) duplicate section DUP SAR for the bit specifying even or odd, and also for a bit specifying which of the frames is required A branch or interrupt rendering unnecessary CPU storage request already made resets th CPU request latch CPU REQ without the access being made. Storage, input circuits (Fig. 10).-A storage address, supplied by either the CPU or a channel (whichever has access), comprises 24 address bits plus a parity bit for each 8 address bits. One address bit selects a storage frame, one selects an even or odd section within it, 14 select a word, 3 select a byte, and 5 are not used (unless extra storage is provided) except that one of the 5 is set to " one " to specify fetching of data from the panel (console). An " invalid address " signal is produced INV ADR if address bits which should not be used are used, or if the odd or even half of a storage frame selected is out of service (indicated by manual switches controlling " ready " lines). An address check signal is produced SAB ADR CHK as a result of a parity check on the address. If the address is invalid and a panel switch is not set or the address has incorrect parity, or if a fetch from the panel is indicated by the address and a panel switch is set, storage access is cancelled and the storage replaced by the panel as a source of data CANC PKF. Two new parity bits for the 14 address bits used for word selection are derived from the full address and the parity bits supplied with it PAR ADJ. Provision is made for comparing the full address with one set up on panel keys ADR COMP. So called " marks " are provided MARKS for selecting bytes in a storage word (e.g. for alteration before restoring), bytes being specifiable individually by a channel (when in control) or during variable field length operations by the CPU, but only in pairs during other CPU operations. A mark parity bit is provided and may be updated during variable field length operations as successive marks are provided. A block of storage may be accessed only if a 4-bit protection key corresponding to it agrees with a key supplied IN KEYS by the channel or CPU, whichever is in control, or if either key is 0000. Each key from a channel or CPU has a parity bit. The CPU key is selected from one of two sources (instruction register and programme status word) and a parity bit for it is derived from a parity bit relating to it and 4 other bits, and said other bits IN KEYS. Storage output circuits (Fig. 11).-Two " tracking " triggers X/Y-W/Z keep track of which accessed data belongs to which request, partially controlling registers X REG, Y REG to indicate the destination of the data and routing various error indications (protection, address parity) to the CPU or channel as appropriate SAP, STR ADR CHK. Whenever neither an even nor an odd section of storage is busy, the " tracking " triggers are checked X/Y-W/Z CHK. In the case of an error signal from this, or from a data parity check in a CPU store (as distinct from fetch) access STR DATA CHK, or from an address parity check in a CPU access STR ADR CHK, a stop clock signal is produced BCU STP CLK. Protection keys from either frame may be accessed OUT KEYS. As mentioned above, data from panel keys may take the place of data from storage, in an output buffer SBOL.

公开(公告)号：DE1524140A1

公开(公告)日：1970-09-10

申请号：DE1524140

申请日：1966-03-19

Applicant: IBM

Inventor： PAUL WISSICK WILLIAM ,  JOHN HASBROUCK LEO ,  RICHARD HOLLERAN CHARLES ,  LISLE SMITH GORDON ,  LOWE MACSORLEY OLIN

IPC: G06F3/023 ,  G06F3/0489 ,  G06F11/00 ,  G06F13/42