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公开(公告)号：ES2140376T3
公开(公告)日：2000-03-01
申请号：ES90480174
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , SCHMIERER QUENTIN GUST
Abstract: A data processing network includes multiple processing devices (18, 20), multiple memory cards (24, 26, 28) of main storage, and a shared interface. Each of the memory cards includes memory arrays (30, 36, 42), an internal register (34, 40, 44) for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected address in the arrays.
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公开(公告)号：DE69033416D1
公开(公告)日：2000-02-10
申请号：DE69033416
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , SCHMIERER QUENTIN GUST
Abstract: A data processing network includes multiple processing devices (18, 20), multiple memory cards (24, 26, 28) of main storage, and a shared interface. Each of the memory cards includes memory arrays (30, 36, 42), an internal register (34, 40, 44) for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected address in the arrays.
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Patent Agency Ranking
公开(公告)号：DE69029648D1
公开(公告)日：1997-02-20
申请号：DE69029648
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , LEVENSTEIN SHELDON BERNARD
IPC: G06F15/16 , G06F13/36 , G06F13/368 , G06F15/17 , G06F15/177 , G06F13/37
Abstract: A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus (70) for transmitting working information between the processors (26, 28) and memory cards. Auxiliary busses, including a command/address bus (72) for commands and address information and a communication bus (74) for status information, are connected to all of the processing devices and slave devices (38, 40, 42, 44) and operate in parallel with the working data bus. A system for distributing control of the working information bus, among all of the master devices and slave devices, includes a grant token and plural select tokens. The grant token, a line connected in common to all devices, permits a device currently controlling the interface to retain control until it completes its transmission. The select tokens, each connected to a uniquely associated slave device and to all of the master devices, consists of a command active line activated by a master device when providing a store or fetch command, a return data line activated by a selected master device to retrieve earlier requested data from a selected slave device, and a buffer full line whereby a slave device with its buffer occupied communicates this fact to all of the master devices.
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公开(公告)号：AU6655390A
公开(公告)日：1991-06-20
申请号：AU6655390
申请日：1990-11-13
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , SCHMIERER QUENTIN GUST
Abstract: A data processing network includes multiple processing devices (18, 20), multiple memory cards (24, 26, 28) of main storage, and a shared interface. Each of the memory cards includes memory arrays (30, 36, 42), an internal register (34, 40, 44) for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected address in the arrays.
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公开(公告)号：DE69033416T2
公开(公告)日：2000-07-06
申请号：DE69033416
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , SCHMIERER QUENTIN GUST
Abstract: A data processing network includes multiple processing devices (18, 20), multiple memory cards (24, 26, 28) of main storage, and a shared interface. Each of the memory cards includes memory arrays (30, 36, 42), an internal register (34, 40, 44) for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected address in the arrays.
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公开(公告)号：DE69029648T2
公开(公告)日：1997-07-17
申请号：DE69029648
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , LEVENSTEIN SHELDON BERNARD
IPC: G06F15/16 , G06F13/36 , G06F13/368 , G06F15/17 , G06F15/177 , G06F13/37
Abstract: A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus (70) for transmitting working information between the processors (26, 28) and memory cards. Auxiliary busses, including a command/address bus (72) for commands and address information and a communication bus (74) for status information, are connected to all of the processing devices and slave devices (38, 40, 42, 44) and operate in parallel with the working data bus. A system for distributing control of the working information bus, among all of the master devices and slave devices, includes a grant token and plural select tokens. The grant token, a line connected in common to all devices, permits a device currently controlling the interface to retain control until it completes its transmission. The select tokens, each connected to a uniquely associated slave device and to all of the master devices, consists of a command active line activated by a master device when providing a store or fetch command, a return data line activated by a selected master device to retrieve earlier requested data from a selected slave device, and a buffer full line whereby a slave device with its buffer occupied communicates this fact to all of the master devices.
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