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Patent Agency Ranking
公开(公告)号：CZ20001437A3
公开(公告)日：2000-07-12
申请号：CZ20001437
申请日：1998-10-14
Applicant: IBM
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公开(公告)号：DE69029648T2
公开(公告)日：1997-07-17
申请号：DE69029648
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , LEVENSTEIN SHELDON BERNARD
IPC: G06F15/16 , G06F13/36 , G06F13/368 , G06F15/17 , G06F15/177 , G06F13/37
Abstract: A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus (70) for transmitting working information between the processors (26, 28) and memory cards. Auxiliary busses, including a command/address bus (72) for commands and address information and a communication bus (74) for status information, are connected to all of the processing devices and slave devices (38, 40, 42, 44) and operate in parallel with the working data bus. A system for distributing control of the working information bus, among all of the master devices and slave devices, includes a grant token and plural select tokens. The grant token, a line connected in common to all devices, permits a device currently controlling the interface to retain control until it completes its transmission. The select tokens, each connected to a uniquely associated slave device and to all of the master devices, consists of a command active line activated by a master device when providing a store or fetch command, a return data line activated by a selected master device to retrieve earlier requested data from a selected slave device, and a buffer full line whereby a slave device with its buffer occupied communicates this fact to all of the master devices.
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公开(公告)号：HU0100013A2
公开(公告)日：2001-05-28
申请号：HU0100013
申请日：1998-10-14
Applicant: IBM
Inventor： BORKENHAGEN JOHN MICHAEL , EICKEMEYER RICHARD JAMES , FLYNN WILLIAM THOMAS , LEVENSTEIN SHELDON BERNARD , WOTTRENG ANDREW HENRY
Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.
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公开(公告)号：DE69029648D1
公开(公告)日：1997-02-20
申请号：DE69029648
申请日：1990-10-31
Applicant: IBM
Inventor： EIKILL RICHARD GLENN , LEVENSTEIN SHELDON BERNARD
IPC: G06F15/16 , G06F13/36 , G06F13/368 , G06F15/17 , G06F15/177 , G06F13/37
Abstract: A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus (70) for transmitting working information between the processors (26, 28) and memory cards. Auxiliary busses, including a command/address bus (72) for commands and address information and a communication bus (74) for status information, are connected to all of the processing devices and slave devices (38, 40, 42, 44) and operate in parallel with the working data bus. A system for distributing control of the working information bus, among all of the master devices and slave devices, includes a grant token and plural select tokens. The grant token, a line connected in common to all devices, permits a device currently controlling the interface to retain control until it completes its transmission. The select tokens, each connected to a uniquely associated slave device and to all of the master devices, consists of a command active line activated by a master device when providing a store or fetch command, a return data line activated by a selected master device to retrieve earlier requested data from a selected slave device, and a buffer full line whereby a slave device with its buffer occupied communicates this fact to all of the master devices.
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